Use of Host System Resources by Memory Controller

• US 20100250836A1
• Filed: 03/22/2010
• Published: 09/30/2010
• Est. Priority Date: 03/25/2009
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Anobit Technologies, Ltd. (Apple Inc.)
• Inventors: Rotbard, Barak, Sokolov, Dotan
• Granted Patent: US 8,832,354 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/1041 Resource optimization
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method for data storage includes, in a system that includes a host having a host memory and a memory controller that is separate from the host and stores data for the host in a non-volatile memory including multiple analog memory cells, storing in the host memory information items relating to respective groups of the analog memory cells of the non-volatile memory. A command that causes the memory controller to access a given group of the analog memory cells is received from the host. In response to the command, a respective information item relating to the given group of the analog memory cells is retrieved from the host memory by the memory controller, and the given group of the analog memory cells is accessed using the retrieved information item.

Claims

1. A method for data storage, comprising:

in a system that includes a host having a host memory and a memory controller that is separate from the host and stores data for the host in a non-volatile memory including multiple analog memory cells, storing in the host memory information items relating to respective groups of the analog memory cells of the non-volatile memory;

receiving from the host a command that causes the memory controller to access a given group of the analog memory cells; and

in response to the command, retrieving from the host memory by the memory controller a respective information item relating to the given group of the analog memory cells, and accessing the given group of the analog memory cells using the retrieved information item.

2. The method according to claim 1, wherein the host memory comprises a Random Access Memory (RAM).

3. The method according to claim 1, wherein the information items comprise read thresholds, and wherein accessing the given group comprises reading the memory cells in the group using one or more read thresholds retrieved from the host memory.

4. The method according to claim 1, wherein the information items comprise erase thresholds, and wherein accessing the given group comprises erasing the memory cells in the given group using one or more erase thresholds retrieved from the host memory.

5. The method according to claim 1, wherein the analog memory cells are programmed using a programming process, wherein the information items comprise parameters of the programming process, and wherein accessing the given group comprises programming the given group using one or more of the parameters that are retrieved from the host memory.

6. The method according to claim 5, wherein the programming process comprises an iterative Programming and Verification (P&

V) process.

7. The method according to claim 1, wherein the information items are indicative of wear levels of the respective groups of the analog memory cells.

8. The method according to claim 1, wherein the information items are indicative of distortion levels in the respective groups of the analog memory cells.

9. The method according to claim 1, wherein the information items specify at least one attribute selected from a set of attributes consisting of a number of programming states, an Error Correction Code (ECC) and an ECC block size to be used in programming the respective groups of the analog memory cells.

10. The method according to claim 1, wherein the information items specify a relation between logical addresses and physical storage locations of the respective groups of the analog memory cells.

11. The method according to claim 1, wherein the information items are indicative of data stored in memory cells that neighbor the respective groups of the analog memory cells.

12. The method according to claim 1, wherein receiving the command comprises communicating between the memory controller and the host over a first physical interface, and wherein retrieving the information item comprises communicating between the memory controller and the host memory over a second physical interface, separate from the first physical interface.

13. The method according to claim 1, wherein retrieving the information item comprises fetching the information item by the memory controller without execution of any operations by the host relating to retrieval of the information item.

14. The method according to claim 1, wherein reception of the command and retrieval of the information item are performed over a common physical interface that connects the memory controller and the host.

15. The method according to claim 14, wherein the common physical interface conforms to one of a NAND interface specification, a Micro-SD (μ

SD) interface specification, an Embedded Multi-Media Card (eMMC) interface specification, a Universal Flash Storage (UFS) interface specification, a Serial Advanced Technology Attachment (SATA) interface specification, a Universal Serial Bus (USB) interface specification and a Peripheral Component Interconnect (PCI) interface.

16. The method according to claim 1, wherein storing the information items and retrieving the information item comprise:

using a hardware signal, sending a request from the memory controller to the host to exchange one or more information items with the memory controller; and

responsively to the request, initiating exchange of the one or more information items by the host.

17. The method according to claim 1, wherein storing the information items comprises sending the information items in responses sent from the memory controller to the host, and wherein retrieving the information item comprises sending the information item in a host command sent from the host to the memory controller.

18. A method for data storage, comprising:

in a system that includes a host and a memory controller that is separate from the host and stores data for the host in a non-volatile memory, assigning a resource of the host for use by the memory controller;

receiving from the host a command that causes the memory controller to access the non-volatile memory; and

in response to the command, accessing the non-volatile memory using the assigned resource of the host.

19. The method according to claim 18, wherein assigning the resource comprises assigning logic circuitry in the host, and wherein accessing the non-volatile memory comprises applying the logic circuitry to process data that is accessed by the command.

20. The method according to claim 18, wherein assigning the resource comprises providing supply voltage to the memory controller by the host.

21. The method according to claim 18, wherein accessing the non-volatile memory comprises reading data from the non-volatile memory, and invoking the host to cancel interference in the read data.

22. The method according to claim 18, wherein accessing the non-volatile memory comprises reading from the non-volatile memory data that is encoded with an Error Correction Code (ECC), and invoking the host to decode the ECC.

23. The method according to claim 22, wherein invoking the host comprises making an attempt to decode the ECC using a first decoder in the memory controller, and, responsively to a failure of the attempt, invoking a second decoder in the host to decode the ECC.

24. The method according to claim 18, wherein assigning the resource comprises assigning memory space in the host, and wherein accessing the non-volatile memory comprises caching multiple pages in the memory space assigned in the host, and copying the multiple cached pages sequentially to the non-volatile memory.

25. A data storage apparatus, comprising:

a first interface, which is configured to communicate with a non-volatile memory that includes multiple analog memory cells;

a second interface, which is configured to communicate with a host having a host memory; and

a processor, which is configured to store in the host memory information items relating to respective groups of the analog memory cells of the non-volatile memory, to receive from the host a command that causes the processor to access a given group of the analog memory cells, and, in response to the command, to retrieve from the host memory a respective information item relating to the given group of the analog memory cells and to access the given group of the analog memory cells using the retrieved information item.

26. The apparatus according to claim 25, wherein the host memory comprises a Random Access Memory (RAM).

27. The apparatus according to claim 25, wherein the information items comprise read thresholds, and wherein the processor is configured to read the memory cells in the given group using one or more read thresholds retrieved from the host memory.

28. The apparatus according to claim 25, wherein the information items comprise erase thresholds, and wherein the processor is configured to erase the memory cells in the given group using one or more erase thresholds retrieved from the host memory.

29. The apparatus according to claim 25, wherein the analog memory cells are programmed using a programming process, wherein the information items comprise parameters of the programming process, and wherein the processor is configured to program the given group using one or more of the parameters that are retrieved from the host memory.

30. The apparatus according to claim 29, wherein the programming process comprises an iterative Programming and Verification (P&

V) process.

31. The apparatus according to claim 25, wherein the information items are indicative of wear levels of the respective groups of the analog memory cells.

32. The apparatus according to claim 25, wherein the information items are indicative of distortion levels in the respective groups of the analog memory cells.

33. The apparatus according to claim 25, wherein the information items specify at least one attribute selected from a set of attributes consisting of a number of programming states and, Error Correction Code (ECC) and an ECC block size to be used in programming the respective groups of the analog memory cells.

34. The apparatus according to claim 25, wherein the information items specify a relation between logical addresses and physical storage locations of the respective groups of the analog memory cells.

35. The apparatus according to claim 25, wherein the information items are indicative of data stored in memory cells that neighbor the respective groups of the analog memory cells.

36. The apparatus according to claim 25, and comprising a third interface that is separate from the second interface, wherein the processor is configured to retrieve the information item by communicating with the host memory over the third interface.

37. The apparatus according to claim 25, wherein the processor is configured to retrieve the information item without execution of any operations by the host relating to retrieval of the information item.

38. The apparatus according to claim 25, wherein the processor is configured to retrieve the information item over the second interface.

39. The apparatus according to claim 38, wherein the second interface conforms to one of a NAND interface specification, a Micro-SD (μ

SD) interface specification, an Embedded Multi-Media Card (eMMC) interface specification, a Universal Flash Storage (UFS) interface specification, a Serial Advanced Technology Attachment (SATA) interface specification, a Universal Serial Bus (USB) interface specification and a Peripheral Component Interconnect (PCI) interface.

40. The apparatus according to claim 25, wherein the processor is configured to request the host, using a hardware signal, to exchange one or more information items with the memory controller, so as to cause the host to initiate exchange of the one or more information items responsively to the request.

41. The apparatus according to claim 25, wherein the processor is configured to send the information items for storage in responses sent to the host, and to receive the retrieved information item in a host command sent from the host.

42. A data storage apparatus, comprising:

a first interface, which is configured to communicate with a non-volatile memory;

a second interface, which is configured to communicate with a host; and

a processor, which is configured to receive from the host a command for accessing the non-volatile memory, and to access the non-volatile memory in response to the command using a pre-assigned resource of the host.

43. The apparatus according to claim 42, wherein the resource comprises logic circuitry in the host, and wherein the processor is configured to apply the logic circuitry to process data that is accessed by the command.

44. The apparatus according to claim 42, wherein the resource comprises supply voltage that is provided by the host.

45. The apparatus according to claim 42, wherein the processor is configured to read data from the non-volatile memory, and to invoke the host to cancel interference in the read data.

46. The apparatus according to claim 42, wherein the processor is configured to read from the non-volatile memory data that is encoded with an Error Correction Code (ECC), and to invoke the host to decode the ECC.

47. The apparatus according to claim 46, wherein the processor is configured to make an attempt to decode the ECC using a first decoder that is coupled to the processor, and, responsively to a failure of the attempt, to invoke a second decoder in the host to decode the ECC.

48. The apparatus according to claim 42, wherein the resource comprises memory space in the host, and wherein the processor is configured to cache multiple pages in the memory space assigned in the host, and to copy the multiple cached pages sequentially to the non-volatile memory.

49. A data storage apparatus, comprising:

a non-volatile memory comprising multiple analog memory cells; and

a processor, which is configured to communicate with a host having a host memory, to store in the host memory information items relating to respective groups of the analog memory cells of the non-volatile memory, to receive from the host a command that causes the processor to access a given group of the analog memory cells, and, in response to the command, to retrieve from the host memory a respective information item relating to the given group of the analog memory cells and to access the given group of the analog memory cells using the retrieved information item.