METHOD AND APPARATUS FOR EVALUATING AND OPTIMIZING A SIGNALING SYSTEM
First Claim
1. An apparatus having (1) a normal mode where the apparatus is to process live data as part of a serial transmission or receipt pipeline and (2) a test mode where the apparatus is to generate test data including a pseudorandom bit sequence, the apparatus comprising:
- a linear shift register having an input to, in the normal mode, receive the live data, the linear shift register also having an output and a storage capacity; and
circuitry to, in the test mode, feed back test data from the output of the linear shift register to the input of the linear shift register, while deterministically modifying at least some of the data;
wherein the pseudorandom bit sequence has a data length significantly greater than the storage capacity of the shift register.
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Accused Products
Abstract
A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.
105 Citations
34 Claims
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1. An apparatus having (1) a normal mode where the apparatus is to process live data as part of a serial transmission or receipt pipeline and (2) a test mode where the apparatus is to generate test data including a pseudorandom bit sequence, the apparatus comprising:
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a linear shift register having an input to, in the normal mode, receive the live data, the linear shift register also having an output and a storage capacity; and circuitry to, in the test mode, feed back test data from the output of the linear shift register to the input of the linear shift register, while deterministically modifying at least some of the data; wherein the pseudorandom bit sequence has a data length significantly greater than the storage capacity of the shift register. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A system, comprising:
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a transmit circuit having a transmit linear shift register and a test loop to generate a transmit pattern based on a repeated pseudorandom bit sequence, the pseudorandom bit sequence generated by the transmit linear shift register having a greater bit length than a capacity of the transmit linear shift register; and a receive circuit having a receive linear shift register and a test loop to generate a receive pattern based on a repeated pseudorandom bit sequence, the pseudorandom bit sequence generated by the receive linear shift register having greater bit length than the receive linear shift register, and a circuit to compare the transmit pattern with the receive pattern; where the transmit shift register and the receive shift register are used in a normal mode for serial transmission of live data between the transmit circuit and the receive circuit, and in a test mode for respective generation of the transmit pattern and the receive pattern. - View Dependent Claims (24, 25, 26)
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27. A method, comprising:
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using a linear shift register in a normal mode to perform one of the serially transmission or the serial receipt of live data; and using the linear shift register in a test mode to generate test data including a pseudorandom bit sequence having a length significantly greater than an instantaneous bit capacity of the shift register, and using a feedback path to provide an input to the linear shift register based on an output of the linear shift register. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34)
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Specification