MEMORY CONTROLLER AND SEMICONDUCTOR MEMORY APPARATUS

• US 20100251075A1
• Filed: 09/16/2009
• Published: 09/30/2010
• Est. Priority Date: 03/30/2009
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: TAKAHASHI, Michiko, Sukegawa, Hiroshi, Sakaue, Kenji
• Application Number:
  US12/560,974
• Publication Number:
  US 20100251075A1
• Time in Patent Office: Days
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence

Abstract

A memory controller that has an error correction number correspondence table that stores an error threshold level in correspondence with an error correction number; an error threshold level storage section that stores an error threshold level for each block; an uncorrected number measurement section that measures an uncorrected number of an error correction for each block; an error threshold level modification section that, each time an uncorrected number of a certain block exceeds a predetermined number, modifies the error threshold level of the block; an encoder that performs encoding processing of data stored in memory cells belonging to each block with an error correction number that is based on an error threshold level and the error correction number correspondence table; and a decoder that performs decoding processing of data.

Claims

1. A memory controller configured to control an error correction for a flash memory section, comprising:

an error correction number correspondence table that stores an error threshold level in correspondence with an error correction number when performing encoding processing of data stored in the flash memory section, the error correction number capable of being increased or decreased, and the flash memory section being composed of a plurality of memory cells that are each classifiable into any one of a plurality of set units;

an error threshold level storage section that stores an error threshold level for each of the set units;

an uncorrected number measurement section that measures an uncorrected number of an error correction for each of the set units;

an error threshold level modification section that, each time the uncorrected number of a certain set unit exceeds a predetermined number, modifies the error threshold level of the relevant set unit that is stored in the error threshold level storage section to a new error threshold level;

an encoder that performs the encoding processing with the error correction number that is based on the error threshold level stored in the error threshold level storage section and the error correction number correspondence table; and

a decoder that performs decoding processing of data that is stored in the flash memory section.

2. The memory controller according to claim 1,

wherein the set unit is comprised by a plurality of memory cells that are classifiable by a reliability parameter that depends on a physical structure of the flash memory section.

3. The memory controller according to claim 1,

wherein the set unit is a block that is an erase unit.

4. The memory controller according to claim 1,

wherein the set unit is a plurality of the blocks.

5. The memory controller according to claim 1,

wherein the set unit is a set unit that comprises the memory cells in which a number of data bits stored in each of the memory cells is the same.

6. The memory controller according to claim 1,

wherein the set unit is a page that is a data read unit.

7. The memory controller according to claim 1,

wherein an initial value of the error threshold level is set for each of the set units.

8. The memory controller according to claim 1,

wherein the predetermined number at which the error threshold level modification section modifies an error threshold level of the set unit differs according to the error threshold level.

9. A semiconductor memory apparatus, comprising:

a flash memory section composed of a plurality of memory cells that are each classifiable into any one of a plurality of set units;

an error correction number correspondence table that stores an error threshold level in correspondence with an error correction number of a memory controller when performing encoding processing of data stored in the flash memory section, the error correction number capable of being increased or decreased;

an error threshold level storage section that stores an error threshold level for each of the set units;

an uncorrected number measurement section that measures an uncorrected number of an error correction for each of the set units;

an error threshold level modification section that, each time the uncorrected number of a certain set unit exceeds a predetermined number, modifies the error threshold level of the relevant set unit that is stored in the error threshold level storage section to a new error threshold level;

an encoder that performs the encoding processing with the error correction number that is based on the error threshold level stored in the error threshold level storage section and the error correction number correspondence table; and

a decoder that performs decoding processing of data that is stored in the flash memory section.

10. The semiconductor memory apparatus according to claim 9,

wherein the set unit is comprised by a plurality of memory cells that are classifiable by a reliability parameter that depends on a physical structure of the flash memory section.

11. The semiconductor memory apparatus according to claim 9,

wherein the set unit is a block that is an erase unit.

12. The semiconductor memory apparatus according to claim 9,

wherein the set unit is a plurality of the blocks.

13. The semiconductor memory apparatus according to claim 9,

wherein the set unit is a set unit that comprises the memory cells in which a number of data bits stored in each of the memory cells is the same.

14. The semiconductor memory apparatus according to claim 9,

wherein the set unit is a page that is a data read unit.

15. The semiconductor memory apparatus according to claim 9,

wherein an initial value of the error threshold level is set for each of the set units.

16. The semiconductor memory apparatus according to claim 9,

wherein the predetermined number at which the error threshold level modification section modifies an error threshold level of the set unit differs according to the error threshold level.

17. A semiconductor memory apparatus, comprising:

a NAND-type flash memory section composed of a plurality of memory cells classifiable into any block that is an erase unit;

an error correction number correspondence table that stores an error threshold level in correspondence with an error correction number of a memory controller when performing encoding processing of data stored in the flash memory section, the error correction number capable of being increased or decreased by the block;

an error threshold level storage section that stores an error threshold level for each of the blocks;

an uncorrected number measurement section that measures an uncorrected number of an error correction for each of the blocks;

an error threshold level modification section that, each time the uncorrected number of a certain block exceeds a predetermined number, modifies an error threshold level of the block that is stored in the error threshold level storage section to a new error threshold level;

an encoder that performs the encoding processing with the error correction number that is based on the error threshold level stored in the error threshold level storage section and the error correction number correspondence table; and

a decoder that performs decoding processing of data that is stored in the flash memory section.