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METHOD FOR FORMING GATE STRUCTURES

  • US 20100252176A1
  • Filed: 05/20/2008
  • Published: 10/07/2010
  • Est. Priority Date: 06/28/2007
  • Status: Active Grant
First Claim
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1. A process for forming a plurality of gate structures, the process comprising:

  • providing a substrate comprising (a) a backing, (b) a plurality of conductive elements disposed on the backing, and (c) a conductive anodization bus parallel to a first edge of the backing, wherein a first conductive element and at least one second conductive element are electrically connected to the anodization bus;

    moving the substrate, wherein the substrate is delivered with a substrate delivery roll and received with a substrate receiving roll, the substrate extends from the substrate delivery roll to the substrate receiving roll, and the substrate passes from the substrate delivery roll to the substrate receiving roll;

    passing the substrate through an anodization station, the anodization station comprising (a) an anodization bath comprising an entry location and an exit location for the substrate, (b) an electrochemical solution retained within the anodization bath, wherein the electrochemical solution has a surface, (c) a cathode located within the electrochemical solution, the plurality of conductive elements positioned between the backing and the cathode, (d) an anode comprising (i) the anodization bus, wherein the anodization bus is positioned above the surface of the electrochemical solution, (ii) the plurality of conductive elements, wherein at least a portion of the plurality of conductive elements are positioned below the surface of the electrochemical solution, and (iii) a plurality of clamps, wherein at least one clamp is in electrical contact with the anodization bus, and (e) a power supply attached to the anode and the cathode; and

    anodizing at least a portion of the surface of the plurality of conductive elements exposed to the electrochemical solution to form a plurality of gate structures comprising a plurality of gate dielectrics adjacent to a plurality of gate electrodes, the plurality of gate electrodes positioned between the plurality of gate dielectrics and the backing.

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