SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20100252832A1
• Filed: 03/29/2010
• Published: 10/07/2010
• Est. Priority Date: 04/02/2009
• Status: Abandoned Application

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: KOEZUKA, Junichi, ASANO, Yuji
• Application Number:
  US12/748,521
• Publication Number:
  US 20100252832A1
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An object is to provide a thin film transistor using an oxide semiconductor layer, in which contact resistance between the oxide semiconductor layer and source and drain electrode layers is reduced and electric characteristics are stabilized. The thin film transistor is formed in such a manner that a buffer layer including a high-resistance region and low-resistance regions is formed over an oxide semiconductor layer, and the oxide semiconductor layer and source and drain electrode layers are in contact with each other with the low-resistance region of the buffer layer interposed therebetween.

Claims

1. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer;

a buffer layer over the oxide semiconductor layer; and

source and drain electrode layers over the buffer layer,

wherein the buffer layer includes a low-resistance region and a high-resistance region,

wherein conductivity of the low-resistance region is higher than conductivity of the oxide semiconductor layer and conductivity of the high-resistance region, and

wherein the low-resistance region is covered with the source and drain electrode layers.

2. The semiconductor device according to claim 1, wherein the buffer layer includes nitrogen.

3. The semiconductor device according to claim 1, wherein a width in a channel direction of the gate electrode layer is smaller than a width in a channel direction of the oxide semiconductor layer.

4. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer;

a buffer layer over the oxide semiconductor layer; and

source and drain electrode layers over the buffer layer,

wherein the buffer layer includes a low-resistance region and a high-resistance region,

wherein conductivity of the low-resistance region is higher than conductivity of the oxide semiconductor layer and conductivity of the high-resistance region,

wherein the low-resistance region is covered with the source and drain electrode layers, and

wherein the buffer layer is a non-single-crystal film formed of an oxide semiconductor.

5. The semiconductor device according to claim 4, wherein the buffer layer includes nitrogen.

6. The semiconductor device according to claim 4, wherein a width in a channel direction of the gate electrode layer is smaller than a width in a channel direction of the oxide semiconductor layer.

7. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer;

a buffer layer over the oxide semiconductor layer; and

source and drain electrode layers over the buffer layer,

wherein the buffer layer includes a low-resistance region and a high-resistance region,

wherein conductivity of the low-resistance region is higher than conductivity of the oxide semiconductor layer and conductivity of the high-resistance region,

wherein the low-resistance region is covered with the source and drain electrode layers, and

wherein an edge portion of the high-resistance region overlaps with the source or drain electrode layer.

8. The semiconductor device according to claim 7, wherein the buffer layer includes nitrogen.

9. The semiconductor device according to claim 7, wherein a width in a channel direction of the gate electrode layer is smaller than a width in a channel direction of the oxide semiconductor layer.

10. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer;

a buffer layer over the oxide semiconductor layer; and

source and drain electrode layers over the buffer layer,

wherein the buffer layer includes a low-resistance region and a high-resistance region,

wherein conductivity of the low-resistance region is higher than conductivity of the oxide semiconductor layer and conductivity of the high-resistance region,

wherein the low-resistance region is covered with the source and drain electrode layers,

wherein the buffer layer is a non-single-crystal film formed of an oxide semiconductor, and

wherein an edge portion of the high-resistance region overlaps with the source or drain electrode layer.

11. The semiconductor device according to claim 10, wherein the buffer layer includes nitrogen.

12. The semiconductor device according to claim 10, wherein a width in a channel direction of the gate electrode layer is smaller than a width in a channel direction of the oxide semiconductor layer.

13. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode layer over a substrate;

forming a gate insulating layer over the gate electrode layer;

forming a first oxide semiconductor film over the gate insulating layer by a sputtering method;

performing heat treatment on the first oxide semiconductor film in an atmospheric atmosphere;

forming a second oxide semiconductor film over the first oxide semiconductor film by a sputtering method;

performing heat treatment on the second oxide semiconductor film in a nitrogen atmosphere;

forming an oxide semiconductor layer and a buffer layer by etching the first oxide semiconductor film and the second oxide semiconductor film;

forming a conductive film over the oxide semiconductor layer and the buffer layer;

forming source and drain electrode layers by etching the conductive film; and

forming a low-resistance region and a high-resistance region by performing heat treatment on an exposed part of the buffer layer in an atmospheric atmosphere,

wherein conductivity of the low-resistance region covered with the source or drain electrode layer is higher than conductivity of the oxide semiconductor layer, and

wherein conductivity of the high-resistance region is lower than conductivity of the low-resistance region.

14. The method for manufacturing a semiconductor device, according to claim 13, wherein the second oxide semiconductor film is formed in an atmosphere of a rare gas and a nitrogen gas.

15. The method for manufacturing a semiconductor device, according to claim 13, further comprising the step of performing reverse sputtering treatment on the second oxide semiconductor film before performing heat treatment in the nitrogen atmosphere.

16. The method for manufacturing a semiconductor device, according to claim 13, wherein an edge portion of the high-resistance region overlaps with the source or drain electrode layer.