LDO With Distributed Output Device

• US 20100253298A1
• Filed: 04/03/2009
• Published: 10/07/2010
• Est. Priority Date: 04/03/2009
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Nonis, Roberto, Da Dalt, Nicola
• Granted Patent: US 8,217,635 B2
• Time in Patent Office: Days
• US Class Current: 323/282
• CPC Class Codes: H03G 1/0005 Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/354 Astable circuits

Abstract

A method and apparatus for supplying independently switched, regulated power to a plurality of loads is disclosed.

Claims

1. An apparatus comprising:

a first input terminal configured to receive a bias voltage, the bias voltage received from a low-dropout voltage regulator (LDO) error amplifier, and a second input terminal configured to receive a supply voltage;

a first output terminal configured to supply a feedback voltage, the feedback voltage supplied to the LDO error amplifier, and a second output terminal configured to supply regulated power to an associated load;

a regulating portion configured to regulate power supplied to the associated load; and

a switching portion configured to enable or disable the load from receiving the regulated power.

2. The apparatus according to claim 1, wherein regulating the power supplied to the associated load includes regulating the power for noise rejection.

3. A digitally controlled ring oscillator comprising the apparatus according to claim 1.

4. The digitally controlled ring oscillator according to claim 3, wherein the associated load comprises an odd number of tri-state inverters connected in parallel, the tri-state inverters being coupled to the second output terminal.

5. The digitally controlled ring oscillator according to claim 3, wherein the digitally controlled oscillator is implemented using electronic circuit technology having a channel length not greater than sixty-five nanometers.

6. The digitally controlled ring oscillator according to claim 5, wherein the digitally controlled oscillator oscillates at a frequency of at least four gigahertz.

7. The digitally controlled ring oscillator according to claim 3, wherein each of the tri-state inverters is comprised of a PMOS device coupled to a first n-type MOS (NMOS) device, the first NMOS device further coupled to a second NMOS device.

8. An apparatus comprising:

a first device configured to supply regulated power to a first load, the first device configured to receive a bias voltage from a low-dropout voltage regulator (LDO) error amplifier, and the first device configured to supply a feedback voltage to the LDO error amplifier; and

a second device configured to supply regulated power to a second load, the second device configured to receive the bias voltage from the LDO error amplifier, and the second device configured to supply a feedback voltage to the LDO error amplifier,

wherein the first device shares a same feedback connection with the second device, and the first device is enabled or disabled independently from the second device.

9. The apparatus according to claim 8, wherein the first device comprises a metal-oxide semi-conductor (MOS) device and the second device comprises a MOS device.

10. The apparatus according to claim 8, wherein regulated power includes power regulated for noise rejection.

11. A digitally controlled ring oscillator comprising the apparatus according to claim 8.

12. The digitally controlled ring oscillator according to claim 11, wherein the first load comprises an odd number of tri-state inverters connected in parallel, the tri-state inverters being coupled to the first device and the second load comprises an odd number of tri-state inverters connected in parallel, the tri-state inverters being coupled to the second device.

13. The digitally controlled ring oscillator according to claim 12, wherein each of the tri-state inverters is comprised of a PMOS device coupled to a first n-type MOS (NMOS) device, the first NMOS device further coupled to a second NMOS device.

14. The digitally controlled ring oscillator according to claim 11, wherein the digitally controlled oscillator is implemented using electronic circuit technology having a channel length not greater than sixty-five nanometers.

15. The digitally controlled ring oscillator according to claim 14, wherein the digitally controlled ring oscillator oscillates at a frequency of at least four gigahertz.

16. A method comprising:

receiving at a plurality of devices a bias voltage, the bias voltage received from a low-dropout voltage regulator (LDO) error amplifier, wherein the plurality of devices share a common bias connection and receive the same bias voltage;

supplying from the plurality of devices a feedback voltage, the feedback voltage supplied to the LDO error amplifier, wherein the plurality of devices share a common feedback connection;

receiving at the plurality of devices a supply voltage, the supply voltage supplied to an input of each of the plurality of devices, wherein the supply voltage has a same voltage level at each input; and

supplying regulated power from one of the plurality of devices to an associated one of a plurality of loads when the one of the plurality of devices is enabled, and not supplying the regulated power to the associated one of the plurality of loads when the one of the plurality of devices is not enabled,

wherein each of the plurality of devices is enabled and disabled independently from the other of the plurality of devices.

17. The method according to claim 16, wherein supplying regulated power includes regulating power for noise rejection.

18. The method according to claim 16, wherein the plurality of devices are metal-oxide-semiconductor (MOS) devices.

19. The method according to claim 16, wherein each one of the plurality of loads is a stage of a digitally controlled ring oscillator, the stage comprising an odd number of tri-state inverters connected in parallel.

20. The method according claim 19, wherein each of the odd number of tri-state inverters is comprised of a PMOS device coupled to a first n-type MOS (NMOS) device, the first NMOS device further coupled to a second NMOS device.

21. The method according to claim 19, the method implemented on an electronic circuit having a channel length technology not greater than sixty-five nanometers.

22. The method according to claim 19, wherein the digitally controlled ring oscillator oscillates at a frequency of at least four gigahertz.