VOLTAGE REGULATOR WITH HIGH ACCURACY AND HIGH POWER SUPPLY REJECTION RATIO
First Claim
1. A voltage regulator circuit, comprising:
- a reference voltage input;
a voltage output;
a first resistor;
a second resistor;
an op-amp having an inverting input, a non-inverting input, and a first op-amp output;
a PMOS transistor; and
a first NMOS transistor;
wherein the reference voltage input is connected to the inverting input, the first op-amp output is connected to a gate of the PMOS transistor, a source of the PMOS transistor is connected to a power supply voltage, a drain of the PMOS transistor is connected to the voltage output and a drain of the first NMOS transistor, a source of the first NMOS transistor is connected to a ground, the voltage output is connected to the first resistor, the first resistor is also connected to the non-inverting input, a second resistor is connected to the first resistor and the ground, and a bias voltage is connected to the gate of the first NMOS transistor so that the first NMOS transistor is in saturation mode.
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Accused Products
Abstract
A voltage regulator circuit with high accuracy and Power Supply Rejection Ratio (PSRR) is provided. In one embodiment, an op-amp with a voltage reference input to an inverting input has the first output connected to a PMOS transistor'"'"'s gate. The PMOS transistor'"'"'s source and drain are each connected to the power supply and the voltage regulator output. The voltage regulator output is connected to an NMOS transistor biased in saturation mode and a series of two resistors. The non-inverting input of the op-amp is connected in between the two resistors for the first feedback loop. The op-amp'"'"'s second output is connected to the gate of the NMOS transistor through an AC-coupling capacitor for the second feedback loop. The op-amp'"'"'s first output can be connected to the power supply voltage through a capacitor to further improve high frequency PSRR. In another embodiment, the role of PMOS and NMOS transistors is reversed.
24 Citations
20 Claims
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1. A voltage regulator circuit, comprising:
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a reference voltage input; a voltage output; a first resistor; a second resistor; an op-amp having an inverting input, a non-inverting input, and a first op-amp output; a PMOS transistor; and a first NMOS transistor; wherein the reference voltage input is connected to the inverting input, the first op-amp output is connected to a gate of the PMOS transistor, a source of the PMOS transistor is connected to a power supply voltage, a drain of the PMOS transistor is connected to the voltage output and a drain of the first NMOS transistor, a source of the first NMOS transistor is connected to a ground, the voltage output is connected to the first resistor, the first resistor is also connected to the non-inverting input, a second resistor is connected to the first resistor and the ground, and a bias voltage is connected to the gate of the first NMOS transistor so that the first NMOS transistor is in saturation mode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A voltage regulator circuit, comprising:
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a reference voltage input; a voltage output; a first resistor; a second resistor; an op-amp having an inverting input, a non-inverting input, and an op-amp output; an NMOS transistor; and a first PMOS transistor; wherein the reference voltage input is connected to the inverting input, the op-amp output is connected to a gate of the NMOS transistor, a source of the NMOS transistor is connected to a ground, a drain of the NMOS transistor is connected to the voltage output and a drain of the first PMOS transistor, a source of the first PMOS transistor is connected to a power supply voltage, the voltage output is connected to the first resistor, the first resistor is also connected to the non-inverting input of the op-amp, a second resistor is connected to the first resistor and the ground, and a bias voltage is connected to the gate of the first PMOS transistor so that the first PMOS transistor is in saturation mode. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A voltage regulator circuit, comprising:
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a reference voltage input; a voltage output; a first resistor; a second resistor; an op-amp having an inverting input, a non-inverting input, a first op-amp output and a second op-amp output; a PMOS transistor; a first NMOS transistor; and a second NMOS transistor; wherein the reference voltage input is connected to the inverting input, the first op-amp output is connected to a gate of the PMOS transistor, a source of the PMOS transistor is connected to a power supply voltage, a drain of the PMOS transistor is connected to the voltage output and a drain of the first NMOS transistor, a source of the first NMOS transistor is connected to a ground, the voltage output is connected to the first resistor, the first resistor is connected to the non-inverting input, a second resistor is connected to the first resistor and the ground, and a bias voltage is connected to the gate of the first NMOS transistor so that the first NMOS transistor is in saturation mode, wherein the bias voltage is supplied by a current source circuit connected to a gate and a drain of the second NMOS transistor, a source of the second NMOS transistor is connected to the ground, the drain of the second NMOS transistor is connected to the gate of the first NMOS transistor through a third resistor, wherein the current source circuit includes a fourth resistor connected to the power supply voltage, and the second op-amp output is connected to the gate of the first NMOS transistor through a capacitor. - View Dependent Claims (19, 20)
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Specification