SEMICONDUCTOR DEVICE AND WAFER WITH A TEST STRUCTURE AND METHOD FOR ASSESSING ADHESION OF UNDER-BUMP METALLIZATION

• US 20100253372A1
• Filed: 12/01/2008
• Published: 10/07/2010
• Est. Priority Date: 12/06/2007
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Desmortreux, David, Bardy, Serge, Le Duc, Philippe, Rousseville, Lucie
• Granted Patent: US 8,395,399 B2
• Time in Patent Office: Days
• US Class Current: 324/705
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/70 Testing of connections between components and printed circuit boards G01R31/68 takes precedence
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Semiconductor device with a patterned pad metal layer and a patterned under-bump metallization layer being mutually electrically connected in a common contact area 22. The semiconductor device includes a first test structure 11 for determining a contact resistance between the patterned metallization layer and the patterned pad metal layer in the common contact areas 22. The first test structure includes a pad metal layer portion 24 and a metallization layer portion 18 being in electrical communication with the pad metal layer portion 24 through the common contact area 22. The first test structure 11 further includes connection areas 14, 16 that are electrically connected with each other substantially via the common contact area 22. Upon application of a current between the connection areas 14, 16 a voltage drop occurs that is representative for a voltage drop over the common contact area 22.

Claims

1. Semiconductor device with a patterned pad metal layer and a patterned under-bump metallization layer being mutually electrically connected in one or more common contact areas, the semiconductor device comprising:

a first test structure for determining a contact resistance between the patterned metallization layer and the patterned pad metal layer in a first one of the common contact areas,

the first test structure including,

a pad metal layer portion being part of the patterned pad metal layer and

including a metallization layer portion being part of the patterned under-bump metallization layer and being in electrical communication with the pad metal layer portion through the first one of the common contact areas,

the first test structure further including,

a first and a second connection area that are electrically connected with each other via a first conductive path that extends substantially through the metallization layer portion, via the first one of the common contact areas and through the pad metal layer portion, and

including a third and a fourth connection area that are electrically connected with each other substantially via a second conductive path that extends via the first one of the common contact areas,

wherein upon application of a current between the first and second connection area a voltage drop between the third and fourth connection area occurs that is representative for a voltage drop over the first one of the common contact areas.

2. Semiconductor device according to claim 1, wherein the first connection area coincides with the third connection area, the second connection area coincides with the fourth connection area, and the first conductive path coincides with the second conductive path and further extends exclusively through the patterned pad metal layer and the patterned under-bump metallization layer.

3. Semiconductor device according to claim 1, wherein the first and second connection area are distinct from the third and fourth connection area.

4. Semiconductor device according to claim 1, the device further comprising, a second test structure defined similarly as the first test structure and having a second one of the common contact areas that is substantially different in size from the first one of the common contact areas.

5. Semiconductor device according to claim 1, the device further comprising, a second test structure defined similarly as the first test structure and having a substantially different geometry of the first conductive path compared to the first test structure so that an electrical layer resistance between the third and the fourth connection area is substantially different in the second test structure compared to that of the first test structure.

6. Semiconductor device according to claim 4, wherein a distance and direction from the first to the second connection area of the first test structure is substantially equal to a distance and direction from the first to the second connection area of the second test structure.

7. Semiconductor device according to claim 4, wherein a distance and direction from the third to the fourth connection area of the first test structure is substantially equal to a distance and direction from the third to the fourth connection area of the second test structure.

8. Semiconductor device according to claim 1, wherein a first imaginary straight line, positioned within the first one of the common contact areas, from a first lead connecting the first one of the common contact areas with the first connection area to a second lead connecting the second connection area with the first one of the common contact areas, has a length that is substantially equal to a length of a second imaginary straight line of maximal length within the first one of the common contact areas.

9. Semiconductor wafer being provided with a semiconductor device according to claim 1.

10. Product including a semiconductor device according to claim 1.

11. Method for assessing adhesion of a patterned under-bump metallization layer on a patterned pad metal layer of a semiconductor wafer, the method comprising:

electrically determining a contact resistance between a part of the patterned under-bump metallization layer and a part of the patterned pad metal layer, and

examining whether the determined contact resistance exceeds a predetermined value.

12. Method according to claim 11, further including,

determining a first resistance by applying a first known electrical current flowing between a first pair of connection areas through a first pad metal layer portion being the part of the patterned pad metal layer, through a first metallization layer portion being the part of the patterned under-bump metallization layer, and via a first common contact area between the first metallization layer portion and the first pad metal layer portion and measuring a first voltage over the first common contact area.

13. Method according to claim 12, wherein the first voltage is measured over the first pair of connection areas.

14. Method according to claim 12, wherein the first voltage is measured over a second pair of connection areas that is distinct from the first pair of connection areas and wherein the connection areas in said second pair are mutually connected through the first pad metal layer portion, the first metallization layer portion, and the first common contact area.

15. Method according to claim 12, further including,

determining a layer resistance inside the first pad metal layer portion and a layer resistance inside the first metallization layer portion, and

determining the contact resistance from the first resistance, the layer resistance inside the first pad metal layer portion and the layer resistance inside the first metallization layer portion.

16. Method according to claim 12, the method further including,

determining a second resistance in a similar way as determining the first resistance, by applying a second known electrical current flowing between a third pair of connection areas through a second pad metal layer portion being part of the patterned pad metal layer, a second metallization layer portion being part of the patterned under-bump metallization layer, and a second common contact area between the second metallization layer portion and the second pad metal layer portion and

measuring a second voltage over the second common contact area, and determining the contact resistance from the first and the second resistance.

17. Method according to claim 16, wherein the second common contact area is substantially different in size from the first common contact area.

18. Method according to claim 16, wherein a geometry of a conductive path between the first pair of connection areas via the first common contact area is substantially different from a geometry of a conductive path between the third pair of connection areas via the second common contact area, so that an electrical layer resistance between the first pair of connection areas contributing to the first voltage is substantially different from an electrical layer resistance between the third pair of connection areas contributing to the second voltage.

19. Method according to claim 11, wherein the patterned under-bump metallization layer is deposited using electroless deposition.

20. Method according to claim 11, wherein the patterned pad metal layer is activated by an activation treatment.

21. Method according to claim 11, wherein the method includes conducting a shear test using a monitor wafer.

22. Method according to claim 11, wherein the semiconductor wafer is a semiconductor wafer according to claim 9.