I/O BUFFER WITH TWICE THE SUPPLY VOLTAGE TOLERANCE USING NORMAL SUPPLY VOLTAGE DEVICES

• US 20100253392A1
• Filed: 10/08/2009
• Published: 10/07/2010
• Est. Priority Date: 04/03/2009
• Status: Active Grant

• Current Assignee: National Sun Yat-sen University
• Original Assignee: National Sun Yat-sen University
• Inventors: Lin, Yan-Liang, Wang, Chua-Chin, KER, Ming-Dou
• Granted Patent: US 7,868,659 B2
• Time in Patent Office: Days
• US Class Current: 327/108
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 19/018592 with a bidirectional operation
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

The invention relates to an I/O buffer with twice the supply voltage tolerance using normal supply voltage devices. The I/O buffer of the invention includes a driver, a first level converter, a gate-controlled circuit and a dynamic source output stage. Signals of the I/O buffer are classified into a first voltage range and a second voltage range. The first voltage range is zero to the normal supply voltage, and the second voltage range is the normal supply voltage to twice the supply voltage. Therefore, the voltage between any two terminals of any of the transistors in the I/O buffer does not exceed the normal supply voltage so that the I/O buffer of the invention can transmit and receive signals with a voltage swing twice as high as the normal power supply voltage using normal supply voltage devices and without gate-oxide reliability problems.

Claims

1. An I/O buffer with twice the supply voltage tolerance using normal supply voltage devices comprising:

a driver, for receiving a mode control signal and a data output signal and generating a first driving signal and a second driving signal;

a first level converter, for receiving the first driving signal to convert a first voltage range of the first driving signal into a second voltage range and output a level translating signal;

a gate-controlled circuit, for receiving the mode control signal and an I/O terminal signal and generating a first gate-controlled signal and a second gate-controlled signal; and

a dynamic source output stage circuit having a first output circuit, a second output circuit and an I/O terminal, the first output circuit and the second output circuit having a plurality of transistors;

wherein the first output circuit is in the second voltage range and controlled by the level translating signal and the first gate-controlled signal;

the second output circuit is in the first voltage range and controlled by the second gate-controlled signal and the second driving signal, such that the voltage across any two terminals of the transistors is not higher than the normal supply voltage and the I/O terminal is used for transmitting or receiving double the supply voltage.

2. The I/O buffer as claimed in claim 1 further comprising an input stage circuit, which has a plurality of transistor and a plurality of inverters for receiving the I/O terminal signal and outputting a data input signal.

3. The I/O buffer as claimed in claim 1, wherein the first output circuit of the dynamic source output stage circuit comprises a first transistor, a second transistor and a third transistor;

the second output circuit comprises a fourth transistor, a fifth transistor and a sixth transistor;

wherein gates of the first transistor and the second transistor are controlled by the level translating signal;

the first transistor and the second transistor are connected to a first connecting point;

the third transistor is electrically disposed between the first connecting point and the I/O terminal, and its gate is controlled by the first gate-controlled signal;

gates of the fifth transistor and the sixth transistor are controlled by the second driving signal;

the fifth transistor and the sixth transistor are connected to a second connecting point; and

the fourth transistor is electrically disposed between the second connecting point and the I/O terminal, and its gate is controlled by the second gate-controlled signal.

4. The I/O buffer as claimed in claim 1, wherein the first voltage range is from 0 to the normal supply voltage, and the second voltage range is from the supply voltage to twice the supply voltage.

5. The I/O buffer as claimed in claim 1, wherein the gate-controlled circuit comprises a second level converter, a first partial circuit and a second partial circuit;

wherein the second level converter is used for receiving the mode control signal to convert a first voltage range of the mode control signal into a second voltage range and output a mode control signal with a high voltage level to the first partial circuit;

wherein the signal of the first partial circuit is within the second voltage range and outputs the first gate-controlled signal; and

wherein the second partial circuit receives the mode control signal, and its signal is within the first voltage range and outputs the second gate-controlled signal.

6. The I/O buffer as claimed in claim 5, wherein the first voltage range of the mode control signal is from 0 to the normal supply voltage;

and the second voltage range of the mode control signal with a high voltage level is from the normal supply voltage to twice the supply voltage.

7. The I/O buffer as claimed in claim 1, wherein when receiving, the gate-controlled circuit receives the mode control signal and the signal of the I/O terminal to generate the first gate-controlled signal and the second gate-controlled signal.

8. The I/O buffer as claimed in claim 1, wherein the first level converter has two transistors respectively connected to a first node and a second node of the first level converter, such that the voltage levels of the first connecting point and the second connecting point are the normal supply voltage.

9. The I/O buffer as claimed in claim 5, wherein the second level converter has two transistors respectively connected to a first node and a second node of the second level converter, such that the voltage levels of the first connecting point and the second connecting point are the normal supply voltage.