DISTRIBUTED FLASH MEMORY STORAGE MANAGER SYSTEMS
First Claim
1. A plurality of memory circuits, each of which is connected to a respective one of a plurality of integrated circuits (“
- ICs”
), each of the ICs being connected to at least one of the other ICs by inter-IC connections so that an IC exchanges memory circuit data with another IC via the inter-IC connections, each of the ICs including memory manager circuitry comprising;
a logic block manager for maintaining a unique global identification (“
ID”
) for each block of data contained in any portion of any of the memory circuits, the global ID including a node ID identifying the IC that is connected to the memory circuit containing that block and a logical block number for that block;
a translator for maintaining a mapping between (1) the logical block number of each block contained in the memory circuit connected to the IC that includes that translator, and (2) a physical portion ID of a portion of that memory circuit that contains that block; and
a driver for receiving the physical portion ID from the translator of the IC that includes that driver and accessing the portion of the memory connected to that IC that is identified by that physical portion ID.
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Accused Products
Abstract
A flash memory storage system may include several modules of flash memory storage manager circuitry, each having some associated flash memory. The modules may be interconnected via the flash memory storage manager circuitry of the modules. The system may be able to write data to and/or read data from the flash memory associated with various ones of the modules by routing the data through the flash memory storage circuitry of the modules. The system may also be able to relocate data for various reasons using such read and write operations. The flash memory storage circuitry of the modules keeps track of where data actually is in the flash memory.
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Citations
20 Claims
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1. A plurality of memory circuits, each of which is connected to a respective one of a plurality of integrated circuits (“
- ICs”
), each of the ICs being connected to at least one of the other ICs by inter-IC connections so that an IC exchanges memory circuit data with another IC via the inter-IC connections, each of the ICs including memory manager circuitry comprising;a logic block manager for maintaining a unique global identification (“
ID”
) for each block of data contained in any portion of any of the memory circuits, the global ID including a node ID identifying the IC that is connected to the memory circuit containing that block and a logical block number for that block;a translator for maintaining a mapping between (1) the logical block number of each block contained in the memory circuit connected to the IC that includes that translator, and (2) a physical portion ID of a portion of that memory circuit that contains that block; and a driver for receiving the physical portion ID from the translator of the IC that includes that driver and accessing the portion of the memory connected to that IC that is identified by that physical portion ID. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
- ICs”
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18. Managing access to a plurality of memory circuits, each of which is connected to a respective one of a plurality of integrated circuits (“
- ICs”
), one of the ICs being connected to at least one of the other ICs by inter-IC connections so that one IC exchanges blocks of memory circuit data with another IC via the inter-IC connections, each of the ICs (“
the source IC”
) including a memory manager comprising;circuitry for maintaining a count of how many times a given IC requests at least one block contained in the memory circuit that is connected to the source IC; and circuitry for transferring a block (“
the transferred block”
), for which the count for one of the other ICs (“
the destination IC”
) exceeds a threshold value, from the memory circuit connected to the source IC to the memory circuit connected to the destination IC. - View Dependent Claims (19, 20)
- ICs”
Specification