DC OFFSET COMPENSATING SYSTEM AND METHOD

• US 20100254491A1
• Filed: 04/01/2009
• Published: 10/07/2010
• Est. Priority Date: 04/01/2009
• Status: Abandoned Application

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Zinser, Richard Louis
• Application Number:
  US12/416,188
• Publication Number:
  US 20100254491A1
• Time in Patent Office: Days
• US Class Current: 375/319
• CPC Class Codes: H04L 25/062 Setting decision thresholds using feedforward techniques only

Abstract

A system for removing a DC-offset component from an input signal is presented. The system includes a sorter to separate positive samples and negative samples of the input signal. The system further includes a positive sample average generator to calculate a positive sample average according to a number of positive samples in the input signal and a negative sample average generator to calculate a negative sample average according to a number of negative samples in the input signal. A balanced average generator is provided for receiving positive and negative sample averages from the positive and negative sample average generators and for generating a reference signal. The system further includes a subtractor for subtracting the reference signal from the input signal to generate a DC-offset compensated output signal.

Claims

1. A DC-offset component compensation system comprising:

a sorter to separate positive samples and negative samples of the input signal;

a positive sample average generator to calculate a positive sample average according to a number of positive samples in the input signal;

a negative sample average generator to calculate a negative sample average according to a number of negative samples in the input signal;

a balanced average generator for receiving positive and negative sample averages from the positive and negative sample average generators and for generating a reference signal;

a subtractor for subtracting the reference signal from the input signal to generate a DC-offset compensated output signal.

2. The system of claim 1, wherein the positive sample average generator comprises a counter to count a number of the positive samples, a positive sample adder to sum the values of the positive samples, and a divider to divide the sum by the number to generate the positive sample average, and

wherein the negative sample average generator comprises a counter to count a number of the negative samples, a negative sample adder to sum the values of the negative samples, and a divider to divide the sum by the number to generate the negative sample average.

3. The system of claim 1, wherein the positive sample average generator comprises a first autoregressive (AR) averaging loop having an autoregressive co-efficient and for receiving the positive samples, wherein the negative sample average generator comprises a second autoregressive (AR) averaging loop having the autoregressive co-efficient and for receiving the negative samples.

4. The system of claim 3, wherein the balanced average generator comprises a summation element for adding the output signals of the first and second AR averaging loops and a mean element for averaging the summed output signals.

5. The system of claim 3 further comprising a multiplier for multiplying the averaged output signals by a gain co-efficient.

6. The system of claim 4, wherein each of the first and second autoregressive (AR) averaging loops comprises a memory register to store the respective positive or negative samples.

7. The system of claim 6, wherein each respective autoregressive (AR) averaging loop further comprises a multiplier to multiply the autoregressive co-efficient and autoregressive coefficient-scaled contents of the respective memory register.

8. The system of claim 1, wherein the positive sample average generator comprises a first fixed point autoregressive (AR) averaging loop having a autoregressive co-efficient and for receiving the positive samples, and

wherein the negative sample average generator comprises a second fixed point autoregressive (AR) averaging loop having the autoregressive coefficient and for receiving the negative samples.

9. The system of claim 8, wherein the balanced average generator comprises a summation element for adding the output signals of the first and second fixed point AR averaging loops, and averaging the summed output signals.

10. The system of claim 9 further comprises multiplying the averaged output signals by the gain co-efficient.

11. The system of claim 9, wherein the first and second fixed point AR averaging loops further comprise left and right bitwise arithmetic shifters and rounding blocks.

12. A digital radio receiver system comprising:

a radio front end to receive a modulated signal;

a digital receiver module comprising an analog to digital converter to digitize the modulated signal and a digital down converter to convert the digitized modulated signal to a baseband signal;

a baseband processor comprising a DC compensating module, a bit detector and synchronization module, and a frame synchronization module, wherein the baseband processor is configured to generate a DC-offset compensated demodulated output signal representing an unbiased estimate of the input signal average;

wherein the digital receiver module and the baseband processor are implemented on a digital processor; and

wherein the DC compensating module implements a sorter to compute separate positive sample and negative sample averages and a balanced average generator to generate a DC-offset compensated output signal.

13. The system of claim 12, wherein the DC compensating module further comprise a positive sample average generator comprising a first autoregressive (AR) averaging loop having a autoregressive coefficient and for receiving the positive samples;

and a negative sample average generator comprising a second autoregressive (AR) averaging loop having the autoregressive coefficient and for receiving the negative samples.

14. The system of claim 13, wherein the balanced average generator comprises a summation element for adding the output signals of the first and second AR averaging loops, a mean element for averaging the summed output signals, and a gain multiplier for multiplying the averaged output signals by the gain coefficient.

15. A method for compensating a DC-offset in a digital receiver, the method comprising:

segregating positive samples and negative samples from an input signal;

computing autoregressive averages of the positive samples and the negative samples;

adding the averages of the positive samples and the negative samples;

calculating a balanced average of the added averages;

subtracting the balanced average from the input signal; and

generating a DC-offset compensated output signal from the subtraction.

16. The method of claim 15, wherein computing the averages comprises using fixed point autoregressive averages.

17. The method of claim 16, wherein using fixed point autoregressive averages comprises left and right bitwise arithmetic shifting the samples.