NETWORK SYNCHRONIZATION OVER IP NETWORKS

• US 20100254499A1
• Filed: 04/06/2009
• Published: 10/07/2010
• Est. Priority Date: 04/06/2009
• Status: Active Grant

• Current Assignee: Arlington Technologies, LLC (Dominion Harbor Enterprises, LLC)
• Original Assignee: Avaya Incorporated
• Inventors: Thavisri, Vipapun
• Granted Patent: US 8,401,007 B2
• Time in Patent Office: Days
• US Class Current: 375/356
• CPC Class Codes: H04J 3/0641 Change of the master or reference, e.g. take-over or failure of the master
• CPC Class Codes: H04J 3/0658 Clock or time synchronisation among packet nodes
• CPC Class Codes: H04J 3/0682 by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
• CPC Class Codes: H04J 3/0697 Synchronisation in a packet node
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways

Abstract

Network timing is derived from the PSTN and distributed through the network to gateways capable of deriving timing from the incoming UDP stream. The derived timing has the correct frequency for voice telephony without using external timing sources or extraneous hardware components. For example, a digital signal processor (DSP) can derive the timing from a timed TDM bus and distribute messages, such as IP messages, to other gateways or port networks. The other gateways and port networks use the incoming stream to extract the timing which is then used to time their TDM bus. The port networks and gateways can also distribute other streams to other gateways in a fan-out type of arrangement. This internally generated timing can be used, for example, for Circuit Emulated Services (CES).

Claims

1. A method for determining clock synchronization in an IP connected network having a plurality of members in one or more domains comprising:

determining a difference between an arrival time of a received packet and outpulsing of a signal to a digital signal processor, in a window;

determining a time to generate window size samples and a time to receive window size samples; and

accumulating a difference which is used to adjust an interrupt timer in at least one member.

2. The method of claim 1, wherein the adjusting of the interrupt timer continues to drive the accumulated difference to zero.

3. The method of claim 1, further comprising when a positive accumulated value difference indicates that an outgoing rate is faster than an incoming rate, a module increases the timer for the interrupt.

4. The method of claim 1, further comprising when a negative accumulated value difference indicates that an outgoing rate is slower than an incoming rate, a module decreases the timer for the interrupt.

5. The method of claim 1, wherein the accumulated value difference is scaled.

6. The method of claim 1, wherein a pre-scaled accumulated value difference is used to prevent momentary reactions to jitter.

7. The method of claim 1, wherein clock synchronization information is sent over one or more inter-gateway connections (IGC) within the IP connected network.

8. The method of claim 1, wherein:

a tandem source is a member within a domain with an IGC derived clock or sync reference;

a slave member has an IGC derived clock or sync reference;

a tandem domain has members having an IGC derived clock or sync reference emanating IGC streams to other members; and

a master domain has members having a DS1 or BRI or clock sync reference emanating IGC streams to other members.

9. One or more means for performing the steps of claim 1.

10. A computer-readable storage media having instructions stored thereon that when executed perform the steps of claim 1.

11. A system for clock synchronization in an IP connected network having a plurality of members in one or more domains comprising:

a controller that;

determines a difference between an arrival time of a received packet and outpulsing of a signal to a digital signal processor, in a window;

determines a time to generate window size samples and a time to receive window size samples; and

accumulates a difference which is stored and used to adjust an interrupt timer in at least one member.

12. The system of claim 11, wherein the adjusting of the interrupt timer continues to drive the accumulated difference to zero.

13. The system of claim 11, further comprising when a positive accumulated value difference indicates that an outgoing rate is faster than an incoming rate, a module increases the timer for the interrupt.

14. The system of claim 11, further comprising when a negative accumulated value difference indicates that an outgoing rate is slower than an incoming rate, a module decreases the timer for the interrupt.

15. The system of claim 11, wherein the accumulated value difference is scaled.

16. The system of claim 11, wherein a pre-scaled accumulated value difference is used to prevent momentary reactions to jitter.

17. The system of claim 11, wherein clock synchronization information is sent over one or more inter-gateway connections (IGC) within the IP connected network.

18. The system of claim 11, wherein:

a tandem source is a member within a domain with an IGC derived clock or sync reference;

a slave member has an IGC derived clock or sync reference;

a tandem domain has members having an IGC derived clock or sync reference emanating IGC streams to other members; and

a master domain has members having a DS1 or BRI or clock sync reference emanating IGC streams to other members.