Digital Output Sensor FIFO Buffer with Single Port Memory

• US 20100257292A1
• Filed: 04/03/2009
• Published: 10/07/2010
• Est. Priority Date: 04/03/2009
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Lee, James M.
• Granted Patent: US 8,156,264 B2
• Time in Patent Office: Days
• US Class Current: 710/52
• CPC Class Codes: G01D 11/00 Component parts of measuring arrangements not specially adapted for a specific variable G01D13/00, G01D15/00 take precedence
• CPC Class Codes: G06F 5/10 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory G06F5/065 takes precedence

Abstract

A digital output sensor includes a sensor module for providing digital data representative of a sensed parameter, a First-In-First-Out (FIFO) memory having a single port memory, and an output port for transmitting the digital data. The digital data from the sensor module is pushed into the FIFO memory buffer via the single memory port, and the digital data is popped out of the FIFO memory buffer via the single memory port for receipt by the output port.

Claims

1. A digital output sensor comprising:

a sensor module for providing digital data representative of a sensed parameter;

an output port for transmitting the digital data; and

a First-In-First-Out (FIFO) memory buffer having a single port memory, wherein the digital data from the sensor module is pushed into the FIFO memory buffer via a single memory port, and wherein the digital data is popped out of the FIFO memory buffer via the single memory port for receipt by the output port.

2. The digital output sensor according to claim 1, further comprising an output holding register operatively coupled between the sensor module and the single port memory, the output holding register for temporarily storing the digital data prior to being pushed into the FIFO memory buffer via the single memory port.

3. The digital output sensor according to claim 1, further comprising an output staging register operatively coupled between the single port memory and the output port, the output staging register for temporarily storing popped digital data from the FIFO memory buffer via the single memory port prior to receipt by the output port.

4. The digital output sensor according to claim 3, further comprising a controller which controls the FIFO memory buffer to pop the digital data to the output staging register substantially upon the output port becoming not busy.

5. The digital output sensor according to claim 1, further comprising:

an output holding register operatively coupled between the sensor module and the single port memory; and

an output staging register operatively coupled between the single port memory and the output port,

wherein when the digital output sensor is in a first mode the output holding register temporarily stores the digital data prior to being pushed into the FIFO memory buffer via the single memory port, and the output staging register temporarily stores the digital data popped from the FIFO memory buffer via the single memory port prior to receipt by the output port, and

wherein when the digital output sensor is in a second mode the FIFO memory buffer is bypassed such that digital data is transferred from the output holding register to the output staging register without passing through the FIFO memory buffer.

6. The digital output sensor according to claim 1, wherein the output port has a data transfer rate that is faster than the sensor module digital data output rate.

7. The digital output sensor according to claim 1, wherein the digital output sensor includes a MEMS accelerometer.

8. The digital output sensor according to claim 1, wherein the FIFO memory buffer is narrower than the width of a data entry to be transferred, such that a plurality of writes to the FIFO memory buffer is performed when pushing a data entry to the FIFO memory buffer, and a plurality of reads from FIFO memory buffer is performed when popping a data entry to the output port.

9. A chip comprising the digital output sensor of claim 1.

10. A method of providing sensor data within a digital output sensor, the method comprising:

providing digital data representative of a sensed parameter;

sending the digital data to a First-In-First-Out (FIFO) memory buffer having a single port memory, wherein the digital data is received and pushed into the FIFO memory buffer via a single memory port; and

popping the digital data out of the FIFO memory buffer via the single memory port for sending to an output port.

11. The method according to claim 10, wherein providing the digital data includes providing the digital data to an output holding register, and wherein sending the digital data to the FIFO memory buffer includes copying the digital data from the output holding register to the FIFO memory buffer via the single memory port.

12. The method according to claim 11, further comprising:

copying the popped digital data from the FIFO memory buffer via the single memory port into an output staging register;

copying the digital data at the output staging register into the output port; and

transmitting the digital data at the output port.

13. The method according to claim 12, wherein copying the popped digital data from the FIFO memory buffer into the output staging register occurs substantially upon the output port becoming not busy.

14. The method according to claim 10, further comprising sensing inertial data by a MEMS accelerometer, and wherein the digital data is representative of sensed inertia.

15. The method according to claim 10, wherein when the digital output sensor is in a first mode the method further includes temporarily storing the digital data in an output holding register prior to the digital data being pushed into the FIFO memory buffer via the single memory port, and temporarily storing the digital data popped from the FIFO memory buffer via the single memory port into an output staging register prior to receipt by the output port, and wherein when the digital output sensor is in a second mode the method further includes bypassing the FIFO memory buffer such that digital data is transferred from the output holding register to the output staging register without passing through the FIFO memory buffer.

16. The method according to claim 10, further comprising transmitting the digital data via the output port, wherein the output port has a data transfer rate that is faster than the sensor module digital data output rate.

17. The method according to claim 10, wherein the FIFO memory buffer is narrower than the width of a data entry to be transferred, such that a plurality of writes to the FIFO memory buffer is performed when pushing a data entry to the FIFO memory buffer, and a plurality of reads from FIFO memory buffer is performed when popping a data entry to the output port.

18. A computer program product for use on a computer system for controlling a digital output sensor having a sensor module for providing digital data representative of a sensed parameter, the digital output sensor further including an output port for transmitting the digital data, and a First-In-First-Out (FIFO) memory buffer having a single port memory, the computer program product comprising a computer usable medium having computer readable program code thereon, the computer readable program code including program code for:

program code for controlling the pushing of the digital data from the sensor module into the FIFO memory buffer via a single memory port; and

program code for controlling the popping of the digital data out of the FIFO memory buffer via the single memory port for receipt by the output port.

19. The computer program product according to claim 18, wherein the digital output sensor further includes an output holding register, the computer program product further comprising:

program code for controlling the sending of the digital data from the sensor module to the output holding register, wherein the program code for controlling the pushing of the digital data includes program code for controlling the copying of the digital data from the output holding register to the FIFO memory buffer via the single memory port.

20. The computer program product according to claim 18, wherein the digital output sensor further includes an output staging register, the computer program product further comprising:

program code for controlling copying of the popped digital data from the FIFO memory buffer via the single memory port into the output staging register.