Method for Managing and Controlling the Low Power Modes for an Integrated Circuit Device

• US 20100257393A1
• Filed: 06/10/2010
• Published: 10/07/2010
• Est. Priority Date: 06/09/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Zhang, Chenmin, Zhuang, Zhiqing, Fadavi-Ardekani, Jalil, Madar, Lawrence John III, Kamal, Soheyla, Bhasin, Vinay Kumar, Rakshani, Vafa James
• Granted Patent: US 8,909,956 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A state machine and an external interface, including its associated input-outputs (IOs), are always powered on and used to manage the chip power modes and power mode transitions. The chip power modes are defined as RUN, HIBERNATE, POWERDOWN, with many more possible with this invention. For example, once the device is in HIBERNATE or POWERDOWN modes, the power supplies to the IC are either reduced, or completely disconnected except for this controller state machine. This invention'"'"'s state machine and control mechanism, in response to some external “wake up event”, will bring the chip to RUN mode by managing the state of the external power supplies through its control interface. The implementation achieves small die size and extreme low power consumption.

Claims

1. A power management unit to manage power modes of an electronic integrated circuit (IC) device, comprising:

a wake up event detection logic circuit configured to trigger a transition between multiple power modes including a first RUN mode and a second RUN mode, and configured to ignore an external event if transitioning from the first RUN mode to the second RUN mode.

2. The power management unit of claim 1, wherein the wake up detection logic circuit is configured to be triggered whenever an input voltage level changes from a high to a low or from a low to a high.

3. The power management unit of claim 1, wherein the first RUN mode is the only operating state in which a processor coupled to the power management unit runs code.

4. The power management unit of claim 1, further comprising a random access memory coupled to the wake up event detection logic and configured to store information about the multiple power modes.

5. The power management unit of claim 1, further comprising an inter-integrated circuit (I2C) bus driver coupled to the wake up event detection logic and configured to drive an external power management unit via an I2C bus.

6. The power management unit of claim 5, wherein the power management unit comprises a data transfer circuit coupled to the wake up event detection logic and configured to write data to an external power management unit using the I2C bus.

7. The power management unit of claim 1, further comprising input and output lines coupled to the wake up event detection logic and configured to communicate with an external processor via an interface.

8. The power management unit of claim 1, further comprising:

a sequencer state machine configured to store voltage levels for the multiple power modes including the first RUN mode, the second RUN mode, a HIBERNATE mode and a POWERDOWN mode;

a timer configured to control wait times during which an external event may trigger a transition between the first RUN mode, the HIBERNATE mode and the POWERDOWN mode;

a control register circuit configured to store information about operating parameters of the power management unit; and

a register file circuit configured to store the settings for the first RUN mode, the HIBERNATE mode and the POWERDOWN mode.

9. The power management unit of claim 8, wherein the state machine is configured to provide zero voltage to the IC device when in the POWERDOWN mode.

10. The power management unit of claim 8, wherein the control register circuit comprises programmable registers controlled by a high speed clock configured to be gated off after the programmable registers have been programmed.

11. The power management unit of claim 10, further comprising an external clock manager to start and stop the high speed clock.

12. The power management unit of claim 10, wherein the control register set is run by the high speed clock.

13. The power management unit of claim 8, wherein the register file circuit is configured to store operating voltage settings for transitions between the first RUN mode, the POWERDOWN mode and the HIBERNATE mode.

14. The power management unit of claim 8, wherein the power management unit is driven by a low frequency clock.

15. The power management unit of claim 14, further including an external clock manager to start and stop the low frequency clock.

16. The power management unit of claim 8, wherein the control register circuit is configured to receive commands from an external processor.

17. The power management unit of claim 8, wherein the sequencer state machine is configured to store commands written by an external host.

18. The power management unit of claim 8, wherein the control register circuit is configured to require input of a security access code to access the control register set.

19. A method to control power modes of an integrated circuit (IC), comprising:

transitioning from one power mode of a plurality of power modes to another power mode, wherein the power modes include a first RUN mode and a second RUN mode; and

if transitioning from the first RUN mode to the second RUN mode, ignoring an external event until the transitioning is complete.

20. The method of claim 19, wherein the plurality of power modes includes a POWERDOWN mode, and wherein the transitioning from the first RUN mode to the POWERDOWN mode includes the steps of:

(a) stopping a clock and a power supply;

(b) counting down to zero from a pre-programmed value;

(c) stopping counting before zero is reached, if an external event is detected;

(d) sending a request to a clock manager, if count is at zero;

(e) waiting for an acknowledgement from the clock manager;

(f) switching to a voltage level corresponding to the POWERDOWN mode, if the count is at zero; and

(g) monitoring for an external event after switching the voltage applied to the IC to the voltage level.

21. The method of claim 19, wherein the plurality of power modes includes a POWERDOWN mode and transitioning from the POWERDOWN mode to the first RUN mode includes the steps of:

(a) detecting a wake up event; and

(b) switching voltage applied to the IC to a voltage level corresponding to the first RUN mode.

22. The method of claim 19, wherein the plurality of power modes includes a HIBERNATE mode and transitioning from the first RUN mode to the HIBERNATE mode includes the steps of:

(a) stopping a clock;

(b) counting down to zero from a pre-programmed value;

(c) stopping counting before zero is reached, if an external event is detected;

(d) sending a request to a clock manager, if count is at zero;

(e) waiting for an acknowledgement from the clock manager;

(f) switching to a voltage level corresponding to the HIBERNATE mode, if the count is at zero; and

(g) monitoring for any external event after switching to the voltage level.

23. The method of claim 19, wherein the plurality of power modes includes a HIBERNATE mode and transitioning from the HIBERNATE mode to the first RUN mode includes the steps of:

(a) detecting a wake up event; and

(b) switching a voltage applied to the IC to a voltage level corresponding to the first RUN mode.

24. The method of claim 19, wherein the plurality of power modes includes a HIBERNATE mode and a POWERDOWN mode and transitioning from the HIBERNATE mode to the POWERDOWN mode includes the steps of:

(a) counting down to zero from a pre-programmed value;

(b) switching a voltage applied to the IC to a voltage level corresponding to the POWERDOWN mode;

(c) ignoring any external event until the switching is complete; and

(d) monitoring for any external event after switching to the voltage level.

25. The method of claim 19, wherein the transitioning from the first RUN mode to the second RUN mode includes:

switching a voltage applied to the IC to a voltage level corresponding to the second RUN mode.

26. The method of claim 19, further comprising:

assigning a respective integrated circuit voltage level range to the multiple power modes including;

the first RUN mode,

a HIBERNATE mode,

a POWERDOWN mode, and

the second RUN mode operating at a voltage range different from that of the first RUN mode;

controlling wait times during which the external event may trigger a transition between the first RUN mode, the HIBERNATE mode and the POWERDOWN mode; and

controlling transitions between the multiple power modes by changing a voltage applied to the IC between respective ranges of voltage levels.