COMPENSATED GATE MISFET AND METHOD FOR FABRICATING THE SAME

• US 20100258848A1
• Filed: 04/08/2010
• Published: 10/14/2010
• Est. Priority Date: 04/08/2009
• Status: Active Grant

• Current Assignee: Efficient Power Conversion Corporation
• Original Assignee: Efficient Power Conversion Corporation
• Inventors: Beach, Robert, Nakata, Alana, Lidow, Alexander, Cao, Jianjun, Zhao, Guang Yuan
• Granted Patent: US 8,350,294 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/66522 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/802 with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors H01L29/806 takes precedence; with one dimensional electron gas H01L29/775; with dimensional electron gas H01L29/778

Abstract

A MISFET, such as a GaN transistor, with low gate leakage. In one embodiment, the gate leakage is reduced with a compensated GaN layer below the gate contact and above the barrier layer. In another embodiment, the gate leakage is reduced by employing a semi-insulating layer below the gate contact and above the barrier layer.

Claims

1. A column III Nitride transistor comprising:

a substrate,

a set of III-N transition layers above the substrate,

a III-N buffer layer above the set of transition layers,

a III-N barrier layer, and

a compensated III-N layer above the barrier layer.

2. The transistor of claim 1, wherein the compensated III-N layer contains acceptor type dopant atoms passivated with hydrogen.

3. The transistor of claim 2, where the acceptor type atoms are selected from the group consisting of Mg, Zn, Be and Ca.

4. A column III Nitride transistor comprising:

a substrate,

a set of III-N transition layers above the substrate,

a III-N buffer layer above the set of transition layers,

a III-N barrier layer, and

a semi-insulating III-N layer above the barrier layer.

5. The transistor of claim 4, wherein the semi-insulating III-N layer contains deep acceptor type dopant atoms.

6. The transistor of claim 5 where the deep acceptor type atoms are selected from the group consisting of C, Fe, Mn, Cr and V.

7. A column III Nitride transistor comprising:

a substrate,

a set of III-N transition layers above the substrate,

a III-N buffer layer above the set of transition layers,

a III-N barrier layer,

a semi-insulating III-N layer above the barrier layer, and

a confinement layer above the semi-insulating III-N layer.

8. The transistor of claim 7, wherein the semi-insulating III-N layer contains deep acceptor type dopant atoms selected from the group consisting of C, Fe, Mn, Cr and V.

9. The transistor of claim 7, wherein the confinement layer is made of SiN, SiO2, Al2O3, HfO2, Ga2O3, or InAlGaN.

10. A compensated gate MISFET transistor comprising:

a barrier layer beneath a gate contact,

a drain contact,

a source contact, and

further comprising one of a compensated or semi-insulating III-N layer between the barrier layer and the gate contact.

11. The transistor of claim 10, further comprising a confinement layer above the one of a compensated or semi-insulating III-N layer.