SEMICONDUCTOR DEVICE

• US 20100258854A1
• Filed: 06/23/2010
• Published: 10/14/2010
• Est. Priority Date: 03/01/2005
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Matsuda, Tetsuo, Saito, Wataru, TOKANO, Kenichi
• Granted Patent: US 7,898,031 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a plurality of first semiconductor regions of a first conduction type formed by disposing a single crystal semiconductor layer of the first conduction type on a surface of the semiconductor substrate and providing a plurality of trenches in the single crystal semiconductor layer, the trenches each having a bottom and sides, a width between the sides being larger as becoming more distant from the bottom, and the plurality of first semiconductor regions being formed at intervals in a direction parallel to the surface; and

a plurality of second semiconductor regions of a second conduction type formed of an epitaxial layer buried in the plurality of trenches,

the plurality of first semiconductor regions having impurity concentrations controlled to increase as becoming more distant from the surface.

2. The semiconductor device according to claim 1, wherein the first semiconductor region is divided in a vertical direction by a unit width to define a plurality of first regions, the second semiconductor region is divided in a vertical direction by the unit width to define a plurality of second regions, and a number of impurity atoms in one of the first regions are substantially equal to that in one of the second regions aligned with the corresponding one of the first regions in a horizontal direction.

3. The semiconductor device according to claim 1, wherein the bottom of the trench reaches the semiconductor substrate.

4. The semiconductor device according to claim 1, wherein the bottom of the trench does not reach the semiconductor substrate, and there is part of the first semiconductor region between the bottom of the each trench and the semiconductor substrate.

5. The semiconductor device according to claim 1, wherein

the plurality of second semiconductor regions each include an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inside the outer portion.

6. The semiconductor device according to claim 5, wherein the outer portion has a substantially constant thickness.

7. The semiconductor device according to claim 5, wherein the outer portion has a substantially constant thickness, and the thickness of the outer portion is less than half the width of a bottom of the trench.