Method for Forming Shielded Gate Trench FET with Multiple Channels

• US 20100258866A1
• Filed: 06/24/2010
• Published: 10/14/2010
• Est. Priority Date: 12/26/2007
• Status: Abandoned Application

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Pan, James
• Application Number:
  US12/823,037
• Publication Number:
  US 20100258866A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

A method of forming a field effect transistor (FET) includes the following steps. A pair of trenches extending into a semiconductor region of a first conductivity type is formed. A shield electrode is formed in a lower portion of each trench. A gate electrode is formed in an upper portion of each trench over but insulated from the shield electrode. First and second well regions of a second conductivity type are formed in the semiconductor region between the pair of trenches such that the first and second well regions are vertically spaced from one another and laterally abut sidewalls of the pair of trenches. The gate electrode and the first shield electrode are formed relative to the first and second well regions such that a channel is formed in each of the first and second well regions when the FET is biased in the on state.

Claims

1-22. -22. (canceled)

23. A method of forming a field effect transistor (FET), the method comprising:

forming a pair of trenches extending into a semiconductor region of a first conductivity type;

forming a shield electrode in a lower portion of each trench;

forming a gate electrode in an upper portion of each trench over but insulated from the shield electrode; and

forming first and second well regions of a second conductivity type in the semiconductor region between the pair of trenches such that the first and second well regions are vertically spaced from one another and laterally abut sidewalls of the pair of trenches,

wherein the gate electrode and the first shield electrode are formed relative to the first and second well regions such that a channel is formed in each of the first and second well regions when the FET is biased in the on state.

24. The method of claim 23 wherein the first well region is laterally directly next to the gate electrode in each trench, and the second well region is laterally directly next to the first shield electrode in each trench.

25. The method of claim 23 further comprising:

forming a shield dielectric lining lower sidewalls and bottom of each trench;

forming a gate dielectric lining upper sidewalls of each trench;

forming source regions of the second conductivity type flanking upper sidewalls of each trench; and

forming a heavy body region of the first conductivity type extending in the first well region.

26. The method of claim 23 wherein the first well region extends over the second well region, and the first region is formed before the second well region.

27. The method of claim 26 wherein the first well region extends over the second well region, the method further comprising:

forming a third well region of the first conductivity type in the semiconductor region between the pair of trenches, the third well region abutting sidewalls of the pair of trenches, the third well region being vertically spaced from the second well region.

28. The method of claim 27 wherein the first well region is laterally directly next to the gate electrode in each trench, and the second and third well regions are laterally directly next to the first shield electrode in each trench.