FRONT END MICRO CAVITY

• US 20100258882A1
• Filed: 04/10/2009
• Published: 10/14/2010
• Est. Priority Date: 04/10/2009
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: MAGNEE, PETRUS H. C., VAN BEEK, JOZEF T. M., KONING, JAN JACOB
• Granted Patent: US 8,580,596 B2
• Time in Patent Office: Days
• US Class Current: 257/415
• CPC Class Codes: B81B 2201/0271 Resonators; ultrasonic resonators
• CPC Class Codes: B81B 2207/015 the micromechanical device and the control or processing electronics being integrated on the same substrate
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate

Abstract

The present invention relates to a method of forming a micro cavity having a micro electrical mechanical system (MEMS) in a process, such as a CMOS process. MEMS resonators are being intensively studied in many research groups and some first products have recently been released. This type of device offers a high Q-factor, small size, high level of integration and potentially low cost. These devices are expected to replace bulky quartz crystals in high-precision oscillators and may also be used as RF filters. The oscillators can be used in time-keeping and frequency reference applications such as RF modules in mobile phones, devices containing blue-tooth modules and other digital and telecommunication devices

Claims

1. A method of forming one or more micro cavities, each micro cavity comprising a micro electrical mechanical system (MEMS), in a process further forming at least one semiconductor component in parallel with the micro cavity and having process steps in common, comprising a step of:

releasing the micro cavity after the formation of the at least one semiconductor component is finished.

2. The method according to claim 1, wherein two or more micro cavities are formed, comprising at least one first cavity being a thick cavity, an at least one second cavity being a thin cavity.

3. The method according to claim 1, comprising the steps of:

providing a substrate, such as a silicon substrate, having a front side comprising the at least one semiconductor component and a back side,

providing a first set of one or more release openings through said backside of the substrate, selected from the group consisting of trench, via, hole, and combinations thereof,

etching through the one or more release openings, thereby releasing the micro cavity.

4. The method according to claim 1, further comprising the steps of:

depositing a hermitic sealing layer on the backside of the substrate to seal the micro cavity formed by etching.

5. The method according to claim 1, wherein the micro cavity comprises a MEMS, and wherein the micro cavity prior to etching comprises a dielectric material, such as an oxide, further comprising the steps of:

depositing a dielectric layer on the front side of the substrate,

depositing a silicon layer on said dielectric layer,

forming a second set of one or more release openings in said silicon layer, selected from the group consisting of trench, via, hole, and combinations thereof,

forming a dielectric structure in said silicon layer and filling the second set of one or more release openings with a dielectric material,

etching the first set of one or more release openings through said back side of the substrate, below the MEMS device, all the way up and through to the dielectric layer, removing the dielectric material in the second set of one or more release openings in said silicon layer, and removing the dielectric structure in said silicon layer, thereby releasing the MEMS.

6. The method according to claim 5, wherein, before etching, the backside of the substrate is grinded down to a pre-determined thickness at the backside of 50-400 μ

m.

7. The method according to claim 1, further comprising the steps of:

providing a substrate, wherein a starting material is a standard thin-film SOI substrate, consisting of a mono-crystalline silicon substrate, a buried silicon oxide layer (BOX) and a thin mono-crystalline silicon layer,

defining a micro cavity comprising a MEMS structure by forming the second set of one or more release openings in said silicon layer, and by forming a dielectric structure in said silicon layer by etching and filling the etched portions that later on in the process will be released,

wherein one or more release openings in said silicon layer are etched down to the BOX, thereby completely isolating the MEMS structure, except for some anchor points,

filling the one or more release openings with silicon oxide,

separating a top surface of the MEMS, followed by covering the entire MEMS structure with a poly silicon layer of a CMOS gate,

wherein an overlap of a capping layer of poly silicon and oxide beyond an edge of the MEMS structure is defined, such that during a subsequent release etch there is some oxide remaining to the sides, and in the same steps in which also normal field isolation and gate patterning are provided.

8. The method according to claim 1, further comprising forming a separation layer,

wherein a first inter-metal dielectric (IMD) layer or LOCOS or STI is used as a separation layer, and/or wherein METAL1 or gate-poly silicon is used as a cap-layer.

9. The method according to claim 1, further comprising providing a passivation layer.

10. The micro cavity comprising:

a MEMS structure, comprising release openings through a substrate on which said micro cavity is formed.

11. The micro cavity according to claim 10, further comprising at least one semiconductor component on a first side of said substrate and a hermitic sealing layer on a second side of said substrate.

14. A band-pass filter comprising a micro cavity according to claim 10.

15. An RF circuit, comprising a micro cavity according to claim 10.

16. A harmonic suppression notch comprising a micro cavity according to claim 10.

17. A phase shifter comprising a micro cavity according to claim 10.

18. An LC circuit comprising a micro cavity according to claim 10.

19. A semiconductor device comprising a micro cavity according to claim 10.

12. An integrated device comprising:

a substrate;

multiple micro cavities on the substrate, each micro cavity comprising a micro electrical mechanical system (MEMS), wherein at least a first micro cavity is a thick micro cavity and at least a second micro second cavity is a thin micro cavity.

13. The integrated device according to claim 12, wherein the thick MEMS is capable of operating at low frequency and the thin MEMS is capable of operating at high frequency.