PATTERNING METHOD AND INTEGRATED CIRCUIT STRUCTURE

• US 20100258913A1
• Filed: 04/09/2009
• Published: 10/14/2010
• Est. Priority Date: 04/09/2009
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lue, Hang-Ting
• Granted Patent: US 8,026,179 B2
• Time in Patent Office: Days
• US Class Current: 257/618
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A patterning method is provided. First, a mask layer and a plurality of first transfer patterns are sequentially formed on a target layer. Thereafter, a plurality of second patterns is formed in the gaps between the first transfer patterns. Afterwards, a plurality of third transfer patterns is formed, wherein each of the third transfer patterns is in a gap between a first transfer pattern and a second transfer pattern adjacent to the first transfer pattern. A portion of the mask layer is then removed, using the first transfer patterns, the second transfer patterns and third transfer patterns as a mask, so as to form a patterned mask layer. Further, a portion of the target layer is removed using the patterned mask layer as a mask.

Claims

1. A patterning method, comprising:

forming a mask layer and a plurality of first transfer patterns sequentially on a target layer;

performing a first conversion process to surfaces of the first transfer patterns, so as to form a plurality of first conversion patterns on the surfaces of the first transfer patterns;

filling a plurality of second transfer patterns in gaps between the first conversion patterns;

removing the first conversion patterns;

performing a second conversion process to surfaces of the first transfer patterns and the second transfer patterns, so as to form a plurality of second conversion patterns on the surfaces of the first transfer patterns and the second transfer patterns;

filling a plurality of third transfer patterns in gaps between the second conversion patterns;

removing the second conversion patterns;

removing a portion of the mask layer, using the first transfer patterns, the second transfer patterns and the third transfer patterns as a mask, so as to form a patterned mask layer; and

removing a portion of the target layer using the patterned mask layer as a mask.

2. The patterning method of claim 1, wherein the target layer is a substrate.

3. The patterning method of claim 1, wherein the target layer is a stacked structure comprising a substrate and a material layer disposed on the substrate.

4. The patterning method of claim 3, wherein the material layer comprises polysilicon or metal.

5. The patterning method of claim 3, wherein the material layer, the first transfer patterns, the second transfer patterns and the third transfer patterns comprise the same material or different materials.

6. The patterning method of claim 1, wherein the first transfer patterns, the second transfer patterns and the third transfer patterns each comprise polysilicon or metal.

7. The patterning method of claim 1, wherein the mask layer comprises TEOS-SiO₂, BPSG, PSG, HSQ, FSG or USG.

8. The patterning method of claim 1, wherein the first conversion process and the second conversion process each comprise an oxidation process, a nitridation process, an oxynitridation process or a metal silicidation process.

9. The patterning method of claim 1, wherein the first conversion patterns and the second conversion patterns comprise the same material or different materials.

10. The patterning method of claim 1, wherein the first conversion patterns and the second conversion patterns each comprise silicon oxide, silicon nitride, silicon oxynitride, metal oxide, metal nitride, metal oxynitride or metal silicide.

11. The patterning method of claim 1, wherein the step of filling the second transfer patterns in the gaps between the first conversion patterns comprises:

forming a first transfer layer to cover the first conversion patterns; and

removing a portion of the first transfer layer to expose tops of the first conversion patterns.

12. The patterning method of claim 11, wherein the step of removing the portion of the first transfer layer comprises performing an etching back process or a CMP process.

13. The patterning method of claim 1, wherein the step of filling the third transfer patterns in the gaps between the second conversion patterns comprises:

forming a second transfer layer to cover the second conversion patterns; and

removing a portion of the second transfer layer to expose tops of the second conversion patterns.

14. The patterning method of claim 13, wherein the step of removing the portion of the second transfer layer comprises performing an etching back process or a CMP process.

15. The patterning method of claim 1, wherein the step of removing the first conversion patterns and the step of removing the second conversion patterns each comprise performing an etching process.

16. A patterning method, comprising:

forming a mask layer and a plurality of first transfer patterns sequentially on a target layer;

forming a plurality of second transfer patterns in gaps between the first transfer patterns;

forming a plurality of third transfer patterns, each of which is in a gap between a first transfer pattern and a second transfer pattern;

removing a portion of the mask layer, using the first transfer patterns, the second transfer patterns and the third transfer patterns as a mask, so as to form a patterned mask layer; and

removing a portion of the target layer using the patterned mask layer as a mask.

17. The patterning method of claim 16, wherein the target layer is a substrate.

18. The patterning method of claim 16, wherein the target layer is a stacked structure comprising a substrate and a material layer disposed on the substrate.

19. The patterning method of claim 18, wherein the material layer comprises polysilicon or metal.

20. The patterning method of claim 16, wherein the first transfer patterns, the second transfer patterns and the third transfer patterns each comprise polysilicon or metal.

21. An integrated circuit structure, comprising:

a target layer, disposed over a substrate and having a plurality of first patterns, a plurality of second patterns and a plurality of third patterns, wherein each first pattern has a line width of L1, each second pattern has a line width of L2, each third pattern has a line width of L3, and L1, L2 and L3 are different from each other, and one first pattern, one second pattern, one third pattern and one second pattern are arranged repeatedly in a sequence.

22. The structure of claim 21, wherein the target layer is a stacked structure comprising a dielectric layer and a material layer disposed on the substrate.

23. The structure of claim 22, wherein the material layer comprises polysilicon or metal.

24. The structure of claim 23, wherein the dielectric layer comprises silicon nitride.