Reduced Susceptibility To Electrostatic Discharge During 3D Semiconductor Device Bonding and Assembly

• US 20100258949A1
• Filed: 04/09/2009
• Published: 10/14/2010
• Est. Priority Date: 04/09/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Henderson, Brian M., Gu, Shiqun, Jalilizeinali, Reza
• Granted Patent: US 8,198,736 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 21/67092 Apparatus for mechanical treatment or grinding or cutting, see the relevant groups in subclasses B24B or B28D
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 23/488 consisting of soldered or bonded constructions bump connectors H01L24/01
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: Y10T 29/53174 Means to fasten electrical component to wiring board, base, or substrate

Abstract

A method to reduce electrostatic discharge susceptibility when assembling a stacked IC device. The method includes coupling a ground plane of a first semiconductor device and a ground plane of a second semiconductor device to substantially a same electrical potential. Active circuitry on the first semiconductor device and active circuitry on the second semiconductor device are electrically coupled after the ground planes are coupled. Electrically coupling the ground planes of the first and the second semiconductor device creates a preferred electrostatic discharge path to ground, thus minimizing potential damage to sensitive circuit elements.

Claims

1. A method to reduce electrostatic discharge (ESD) when assembling a stacked IC device, comprising:

coupling a ground plane of a first semiconductor device and a ground plane of a second semiconductor device to substantially a same electrical potential; and

electrically coupling active circuitry on the first semiconductor device and active circuitry on the second semiconductor device after the ground planes are coupled.

2. The method of claim 1, in which a threshold difference in an electrical potential between the ground planes of the first semiconductor device and the second semiconductor device is less than a harmful electrical potential that damages the active circuitry.

3. The method of claim 1, in which the coupling comprises contacting at least one conductive pad, electrically coupled to the ground plane of the first semiconductor device, with an electrical contact probe of a pick-and-place (PnP) head.

4. The method of claim 1, in which the coupling comprises affixing a conductive edge clip of a pick-and-place (PnP) chuck to at least one conductive pad, electrically coupled to the ground plane of the first semiconductor device.

5. The method of claim 1, in which the coupling comprises affixing the first semiconductor device to a carrier with a temporary electrically conductive adhesive coupled to the ground plane of the first semiconductor device and thereby placing the ground plane of the first semiconductor device at the substantially same electrical potential.

6. The method of claim 1, in which coupling the ground planes comprises contacting at least one ground plane conductive contact bump of the first semiconductor device with at least one ground plane conductive contact bump of the second semiconductor device.

7. A system to assemble stacked IC devices with reduced electrostatic discharge (ESD) susceptibility, comprising:

a movable pick-and-place (PnP) chuck configured to carry at least a first semiconductor device containing one or more integrated circuits, the first semiconductor device including a ground plane and active circuitry; and

a movable PnP head configured to carry a second semiconductor device comprising a ground plane and active circuitry,

wherein the system is configured to electrically couple the ground planes of the first and second semiconductor devices to substantially a same electrical potential prior to electrically coupling the active circuitry of the first and second semiconductor devices.

8. The system of claim 7, in which the PnP head comprises an electrical contact probe configured to couple with the ground plane on the first semiconductor device prior to electrically coupling the active circuitry of the first and second semiconductor devices.

9. The system of claim 7, in which the PnP chuck comprises a conductive edge clip configured to couple to the ground plane of the first semiconductor device to put the first semiconductor device ground plane and the PnP chuck at substantially the same electrical potential prior to electrically coupling the active circuitry of the first and second semiconductor devices.

10. A first semiconductor device for assembly with a second semiconductor device to create a stacked IC device, comprising:

at least one conductive pad coupled to a ground plane of the first semiconductor device, the at least one conductive pad enabling placing the ground plane of the first semiconductor device and the ground plane of the second semiconductor device at substantially a same electrical potential before coupling an active circuit on the first semiconductor device to an active circuit on the second semiconductor device of the stacked IC device.

11. The first semiconductor device of claim 10, in which the at least one conductive pad of the first semiconductor device is configured to be contacted by a contact probe of a pick-and-place (PnP) head to place the ground plane of the first semiconductor device and the ground plane of the second semiconductor device at substantially the same electrical potential before coupling the active circuit on the first semiconductor device to the active circuit on the second semiconductor device.

12. The first semiconductor device of claim 11, in which the first semiconductor device is a wafer and the second semiconductor device is a chip.

13. The first semiconductor device of claim 11, in which the first semiconductor device is a chip and the second semiconductor device is a chip.

14. The first semiconductor device of claim 10, in which the at least one conductive pad on the first semiconductor device is configured to be contacted by a conductive edge clip of a pick-and-place (PnP) chuck to place the ground planes of the first semiconductor device and the second semiconductor device at substantially the same electrical potential before coupling the active circuit on the first semiconductor device to the active circuit on the second semiconductor device.

15. The first semiconductor device of claim 14, in which the first semiconductor device comprises a wafer, and the at least one conductive pad is coupled to ground planes of a plurality of chips on the wafer.

16. The first semiconductor device of claim 10, in which the at least one conductive pad of the first semiconductor device is configured to be contacted by a ground plane conductive pad of the second semiconductor device, to place the ground planes of the first and second semiconductor devices at substantially the same electrical potential before coupling the active circuit on the first semiconductor device to the active circuit on the second semiconductor device.

17. The first semiconductor device of claim 16, in which the at least one conductive pad of the first semiconductor device is larger than active circuitry conductive pads on the first semiconductor device.

18. The first semiconductor device of claim 10, in which the at least one conductive pad is provided in a scribe lane.

19. The first semiconductor device of claim 10, in at least one of the first and second semiconductor devices does not include ESD protection circuitry.

20. A first semiconductor device for assembly with a second semiconductor device to create a stacked IC device, comprising:

means for reducing susceptibility to electrostatic discharge (ESD) coupled to a ground plane of the first semiconductor device, the reducing means enabling placing of the ground plane of the first semiconductor device and a ground plane of the second semiconductor device at substantially a same electrical potential before coupling active circuitry of the first semiconductor device to active circuitry of the second semiconductor device.