PACKAGE WITH SEMICONDUCTOR DEVICE AND INTEGRATED CIRCUIT MOUNTED THEREIN AND METHOD FOR MANUFACTURING SUCH PACKAGE

• US 20100258950A1
• Filed: 08/20/2009
• Published: 10/14/2010
• Est. Priority Date: 04/14/2009
• Status: Abandoned Application

• Current Assignee: MEMSensing Microsystems (Suzhou, China) Co., Ltd.
• Original Assignee: MEMSensing Microsystems (Suzhou, China) Co., Ltd.
• Inventors: Mei, Jia-Xin, Hu, Wei, LI, GANG
• Application Number:
  US12/544,415
• Publication Number:
  US 20100258950A1
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2203/019 characterised by the material or arrangement of seals between parts
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/29101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/812 Applying energy for connecting
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/838 Bonding techniques
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/0133 : Ternary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A multichip package includes a first chip and a second chip coupled with the first chip. The first chip includes a first base with a semiconductor device mounted on one side of the first base, a first electrical connection unit, a first bonding ring surrounding the semiconductor device, a first insulating layer formed on the other side of the first base and a first external bonding portion formed on the first insulating layer. The first external bonding portion is electrically connected to the first electrical connection unit. The second chip includes an integrated circuit corresponding to the semiconductor device, a second electrical connection unit fusing with the first electrical connection unit, and a second bonding ring fusing with the first bonding ring in order to form a hermetic cavity surrounding the semiconductor device, the integrated circuit, the first electrical connection unit and the second electrical connection unit.

Claims

1. A package with a semiconductor device and an integrated circuit mounted therein comprising:

a first chip having a first base with the semiconductor device mounted on one side of the first base, a first electrical connection unit, a first bonding ring surrounding the semiconductor device, a first insulating layer formed on the other side of the first base and a first external bonding portion formed on the first insulating layer under a condition that the first external bonding portion is electrically connected to the first electrical connection unit; and

a second chip coupled to the first chip and comprising the integrated circuit corresponding to the semiconductor device, a second electrical connection unit fusing with the first electrical connection unit, and a second bonding ring fusing with the first bonding ring in order to form a hermetic cavity surrounding the semiconductor device, the integrated circuit, the first electrical connection unit and the second electrical connection unit.

2. The package as claimed in claim 1, wherein the first external bonding portion comprises a first electrical connecting layer disposed on the first insulating layer and a first additional electrical connecting layer connecting the first electrical connecting layer and the first electrical connection unit.

3. The package as claimed in claim 2, wherein the first external bonding portion comprises a first additional UBM layer formed on the first electrical connecting layer and a first solder layer formed on the first additional UBM layer, the first solder layer comprising a solder ball electrically connected to the first electrical connection unit under a condition that the solder ball is adapted for being soldered to an external board.

4. The package as claimed in claim 2, wherein the first electrical connection unit comprises a first bonding pad connecting the first external bonding portion, the package further defining a through hole extending through the first chip and corresponding to the first bonding pad, the first bonding pad being exposed to the outside through the through hole.

5. The package as claimed in claim 3, wherein the first additional UBM layer comprises an adhesion layer formed on the first electrical connecting layer, a diffusion barrier layer formed on the adhesion layer, a wetting layer formed on the diffusion barrier layer, and an oxidation barrier layer formed on the wetting layer.

6. The package as claimed in claim 1, wherein the first insulating layer is made of silica or silicon nitride.

7. The package as claimed in claim 1, wherein lateral sides of the first and the second chips are align with each other.

8. A package with a semiconductor device and an integrated circuit mounted therein comprising:

a first chip having the semiconductor device, a first electrical connection unit and a first bonding ring surrounding the semiconductor device; and

a second chip coupled to the first chip and comprising a second base with the integrated circuit mounted on one side of the second base, a second electrical connection unit and a second bonding ring, the integrated circuit being opposite to and corresponding to the semiconductor device, the first and the second electrical connection units being fused with each other, similarly, the second bonding ring fusing with the first bonding ring in order to form a hermetic cavity surrounding the semiconductor device, the integrated circuit, the first electrical connection unit and the second electrical connection unit;

wherein the second chip further comprises a second insulating layer formed on the other side of the second base and a second external bonding portion disposed on the second insulating layer under a condition that the second external bonding portion is electrically connected to the second electrical connection unit.

9. The package as claimed in claim 8, wherein the second external bonding portion comprises a second electrical connecting layer disposed on the second insulating layer and a second additional electrical connecting layer connecting the second electrical connecting layer and the second electrical connection unit.

10. The package as claimed in claim 9, wherein the second external bonding portion comprises a second additional UBM layer formed on the second electrical connecting layer and a second solder layer formed on the second additional UBM layer, the second solder layer comprising a solder ball electrically connected to the second electrical connection unit under a condition that the solder ball is adapted for being soldered to an external board.

11. The package as claimed in claim 9, wherein the second electrical connection unit comprises a second bonding pad connecting the second external bonding portion, the package further defining a through hole extending through the second chip in order that the second bonding pad is exposed to the outside through the through hole.

12. The package as claimed in claim 10, wherein the second additional UBM layer comprises an adhesion layer disposed on the second electrical connecting layer, a diffusion barrier layer formed on the adhesion layer, a wetting layer formed on the diffusion barrier layer, and an oxidation barrier layer formed on the wetting layer.

13. The package as claimed in claim 8, wherein the second insulating layer is made of silica or silicon nitride.

14. A method for manufacturing a package comprising steps of:

a) providing a first wafer and a second wafer, the first wafer being provided with a first base, a semiconductor device mounted on one side of the first base, a first bonding pad and a first bonding ring enclosing the semiconductor device;

the second wafer being provided with a second base, an integrated circuit mounted on one side of the second base, a second bonding pad and a second bonding ring enclosing the integrated circuit;

b) coupling the first and the second wafers with each other under a condition that the first and the second bonding pads are electrically connected with each other, and the first and the second bonding rings fuse with each other to jointly form a hermetic cavity which surrounds the semiconductor device, the integrated circuit, the first bonding pad and the second bonding pad;

c) defining a first through hole on the other side of the first base with the first through hole reaching the first bonding pad;

or defining a second through hole on the other side of the second base with the second through hole reaching the second bonding pad;

d) depositing a first insulating layer on the other side of the first base and then etching undesired portions of the first insulating layer to expose the first bonding pad through the first through hole;

or depositing a second insulating layer on the other side of the second base and then etching undesired portions of the second insulating layer to expose the second bonding pad through the second through hole;

e) forming a first external bonding portion on the first insulating layer under a condition that the first external bonding portion is electrically connected to the first bonding pad for electrically connecting to an external circuit;

or forming a second external bonding portion on the second insulating layer under a condition that the second external bonding portion is electrically connected to the second bonding pad for electrically connecting to an external circuit; and

f) cutting out the first and the second wafers simultaneously to obtain each independent package.

15. The method for manufacturing a package as claimed in claim 14, wherein the first external bonding portion comprises a first electrical connecting layer formed on the first insulating layer and a first additional electrical connecting layer connecting the first electrical connecting layer and the first bonding pad;

the second external bonding portion comprising a second electrical connecting layer formed on the second insulating layer and a second additional electrical connecting layer connecting the second electrical connecting layer and the second bonding pad.

16. The method for manufacturing a package as claimed in claim 15, wherein the first external bonding portion comprises a first additional UBM layer formed on first electrical connecting layer and a first solder layer formed on the first additional UBM layer, and wherein the first solder layer comprises a solder ball electrically connected to the first bonding pad under a condition that the solder ball is adapted for being soldered to the external circuit;

the second bending portion comprising a second additional UBM layer formed on the second electrical connecting layer and a second solder layer formed on the second additional UBM layer, and wherein the second solder layer comprises a solder ball electrically connected to the second bonding pad under a condition that the solder ball is adapted for being soldered to the external circuit.

17. The method for manufacturing a package as claimed in claim 16, wherein the first additional UBM layer comprises a first adhesion layer disposed on the first electrical connecting layer, a first diffusion barrier layer formed on the first adhesion layer, a first wetting layer formed on the first diffusion barrier layer, and a first oxidation barrier layer formed on the first wetting layer;

similarly, the second additional UBM layer comprising a second adhesion layer disposed on the second electrical connecting layer, a second diffusion barrier layer formed on the second adhesion layer, a second wetting layer formed on the second diffusion barrier layer, and a second oxidation barrier layer formed on the second wetting layer.

18. The method for manufacturing a package as claimed in claim 14, wherein neither the first nor the second insulating layer is made of silica or nitride.

19. The method for manufacturing a package as claimed in claim 14, wherein corresponding lateral sides of the first and the second chips are aligned with each other.

20. The method for manufacturing a package as claimed in claim 14, wherein the first and the second through holes are of column shape or conoid shape.