VOLTAGE CONVERSION AND INTEGRATED CIRCUITS WITH STACKED VOLTAGE DOMAINS

• US 20100259299A1
• Filed: 04/13/2009
• Published: 10/14/2010
• Est. Priority Date: 04/13/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dennard, Robert H., Ji, Brian L.
• Granted Patent: US 8,174,288 B2
• Time in Patent Office: Days
• US Class Current: 326/80
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03K 19/01806 Interface arrangements
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 3/00 Circuits for generating electric pulses; Monostable, bistable or multistable circuits H03K4/00 takes precedence; for digital function generators in computers G06F1/02
• CPC Class Codes: H03K 3/356139 with synchronous operation

Abstract

An integrated circuit (IC) system includes a plurality of ICs configured in a stacked voltage domain arrangement such that a low side supply rail of at least one of ICs is common with a high side supply rail of at least another of the ICs; a reversible voltage converter coupled to power rails of each of the plurality of ICs, the reversible voltage converter configured for stabilizing individual voltage domains corresponding to each IC; and one or more data voltage level shifters configured to facilitate data communication between ICs operating in different voltage domains, wherein an input signal of a given logic state corresponding to one voltage in a first voltage domain is shifted to an output signal of the same logic state at another voltage in a second voltage domain.

Claims

1. An integrated circuit (IC) system, comprising:

a plurality of ICs configured in a stacked voltage domain arrangement with respect to an external power supply voltage such that a low side supply rail of at least one of the plurality of ICs is common with a high side supply rail of at least another of the plurality of the ICs;

a reversible voltage converter coupled to power rails of each of the plurality of ICs, the voltage converter configured for stabilizing individual voltage domains corresponding to each IC; and

one or more data voltage level shifters configured to facilitate data communication between ICs operating in different voltage domains, wherein an input signal of a given logic state corresponding to one voltage in a first voltage domain is shifted to an output signal of the same logic state at another voltage in a second voltage domain.

2. The system of claim 1, wherein:

for a total number, N, of stacked ICs, there are N voltage domains in the system;

the plurality of ICs are serially stacked between a high voltage rail at a voltage value of N*V_dd and ground, wherein V_dd represents a nominal operating voltage of a given one of the ICs; and

wherein a lowest voltage domain operates between V_dd and ground, a next lowest voltage domain operates between 2*V_dd and V_dd, and wherein a highest voltage domain operates between N*V_dd and (N−

1)*V_dd.

3. The system of claim 1, wherein the one or more data voltage level shifters further comprise:

an inverter operating in the first voltage domain that receives the input signal of a given logic state;

a cross-coupled latch device operating in the second voltage domain that produces the output signal of the same logic state; and

a capacitor that dynamically couples an inverted value of the input signal to a first node of the latch device, such that a second, complementary node of the latch device corresponds to shifted output data for use in the second voltage domain.

4. The system of claim 3, wherein the one or more data voltage level shifters operate to communicate transitions in data from logic high to logic low and vice versa across different voltage domains.

5. The system of claim 1, wherein the reversible voltage converter is configured to selectively operate in at least:

a first power mode in which each of the plurality of ICs utilize substantially the same current, a second power mode in which each of the plurality of ICs operate at substantially the same voltage, and a third power mode in which the plurality of ICs dissipate substantially the same amount of power.

6. The system of claim 3, wherein the first, second and third power modes depend upon a clock frequency of the switched capacitor voltage converter.

7. The system of claim 1, wherein the plurality of ICs are disposed on a common chip.

8. The system of claim 7, wherein the common chip comprises one of silicon-on-insulator (SOI) technology and triple well bulk technology.

9. The system of claim 1, wherein the plurality of ICs comprise separate chips that are vertically stacked with respect to one another.

10. A data voltage level shifting apparatus, comprising:

an inverter that receives an input signal of a given logic state, the input signal originating from a first integrated circuit device operating in a first voltage domain;

a cross-coupled latch device that produces an output signal of the same logic state, the output signal for use by a second integrated circuit device operating in a second voltage domain; and

a capacitor that dynamically couples an inverted value of the input signal to a first node of the latch device, such that a second, complementary node of the latch device corresponds to shifted output data for use in the second voltage domain.

11. The apparatus of claim 10, wherein the data voltage level shifting apparatus operates to communicate transitions in data from logic high to logic low and vice versa across different voltage domains.

12. The apparatus of claim 10, wherein the second voltage domain is higher than the first voltage domain.

13. The apparatus of claim 10, wherein the first voltage domain is higher than the second voltage domain.

14. A reversible, switched capacitor voltage conversion apparatus, comprising:

a plurality of individual unit cells coupled to one another in stages, with each unit cell comprising multiple sets of inverter devices arranged in a stacked configuration, such that each set of inverter devices operates in separate voltage domains wherein outputs of inverter devices in adjacent voltage domains are capacitively coupled to one another; and

wherein outputs of at least one of the plurality of individual unit cells serve as corresponding inputs for at least another one of the plurality of individual unit cells.

15. The apparatus of claim 14, wherein outputs of a last of the plurality of individual unit cells comprise inputs to a first of the plurality of individual unit cells in a ring oscillator type structure.

16. The apparatus of claim 14, wherein inputs to a first of the plurality of individual unit cells comprise control signals.

17. The apparatus of claim 15, wherein the inputs to the first of the plurality of individual unit cells are prevented from allowing simultaneous conduction of a PFET device and an NFET device of inverter device in each voltage domain.

18. The apparatus of claim 17, wherein each input to the first of the plurality of individual unit cells is coupled to a buffer device operating in the corresponding voltage domain, with an output of each buffer device serving as inputs to the inverter device in the corresponding voltage domain.

19. The apparatus of claim 18, further comprising, for each voltage domain, a first buffer device coupled to a PFET of the inverter device and a second buffer device coupled to an NFET of the inverter device.

20. The apparatus of claim 18, wherein the first and second buffer devices each comprise an inverter pair where a first of the inverter pair has a larger NFET/PFET device width ratio and a second of the inverter pair has a larger PFET/NFET device width ratio.

21. A method of regulating current, power and voltage levels of an integrated circuit (IC) system, the method comprising:

configuring a plurality of ICs in a stacked voltage domain arrangement with respect to an external power supply voltage such that a low side supply rail of at least one of the plurality of ICs is common with a high side supply rail of at least another of the plurality of the ICs;

coupling a reversible voltage converter to power rails of each of the plurality of ICs, the voltage converter configured for stabilizing individual voltage domains corresponding to each IC; and

setting a clock frequency of the reversible voltage converter so as to selectively operate in the IC system in at least, other than a first power mode in which each of the plurality of ICs utilize substantially the same current;

a second power mode in which each of the plurality of ICs operate at substantially the same voltage, and a third power mode in which the plurality of ICs dissipate substantially the same amount of power.

22. The method of claim 21, wherein for a total number, N, of stacked ICs, there are N voltage domains in the system.

23. The method of claim 22, wherein:

the plurality of ICs are serially stacked between a high voltage rail at a voltage value of N*V_dd and ground, wherein V_dd represents a nominal operating voltage of a given one of the ICs; and

wherein a lowest voltage domain operates between V_dd and ground, a next lowest voltage domain operates between 2*V_dd and V_dd, and wherein a highest voltage domain operates between N*V_dd and (N−

1)*V_dd.

24. The method of claim 21, further comprising configuring one or more data voltage level shifters configured to facilitate data communication between ICs operating in different voltage domains, wherein an input signal of a given logic state corresponding to one voltage in a first voltage domain is shifted to an output signal of the same logic state at another voltage in a second voltage domain.

25. A method of implementing data voltage level shifting between integrated circuit devices, the method comprising:

coupling an input signal of a given logic state to an inverter operating in a first voltage domain, the input signal originating from a first integrated circuit device operating in the first voltage domain;

generating an output signal of the same logic state from a cross-coupled latch device operating in a second voltage domain, the output signal for use by a second integrated circuit device operating in the second voltage domain; and

dynamically coupling an inverted value of the input signal to a first node of the latch device through a capacitor, such that a second, complementary node of the latch device corresponds to shifted output data for use in the second voltage domain.