DATA TRANSFER CIRCUIT AND METHOD WITH COMPENSATED CLOCK JITTER

• US 20100259310A1
• Filed: 04/06/2010
• Published: 10/14/2010
• Est. Priority Date: 04/08/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: PARK, Kwang Il, KWAK, Sang Hyup, BAE, Seung Jun, KIM, Young-Sik
• Granted Patent: US 8,269,537 B2
• Time in Patent Office: Days
• US Class Current: 327/288
• CPC Class Codes: H03K 2005/0013 Avoiding variations of delay due to power supply
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle

Abstract

A data I/O interface for an integrated circuit device includes a noise detector receiving a power supply voltage, detecting a power supply voltage noise component, and providing a clock delay control signal in response to detected power supply voltage noise component. The data I/O interface also includes a clock delay circuit providing a delayed clock signal in response to the clock delay control signal, and a data transfer circuit powered by the power supply voltage and providing output data synchronously with the delayed clock signal.

Claims

1. An integrated circuit device, comprising:

a noise detector circuit configured to receive a power supply voltage, detect a power supply voltage noise component from the power supply voltage, and provide a clock delay control signal in response to the detected power supply voltage noise component;

a clock delay circuit configured to receive a clock signal and delay the clock signal in response to the clock delay control signal to generate a delayed clock signal; and

a data transfer circuit configured to receive input data and provide output data corresponding to the input data, wherein the data transfer circuit is powered by the power supply voltage and provides the output data synchronously with the delayed clock signal.

2. The integrated circuit device of claim 1, wherein the power supply voltage noise component is amplitude jitter corresponding to amplitude variations in the power supply voltage.

3. The integrated device of claim 2, wherein the noise detector comprises:

a noise pass filter configured to receive the power supply voltage and provide a power supply voltage filtered noise response; and

a noise amplifier configured to receive the power supply voltage filtered noise response and provide the clock delay control signal in response to the power supply voltage noise response.

4. The integrated circuit device of claim 2, wherein the clock delay circuit is a voltage controlled delay line receiving the clock signal and providing the delayed clock signal in response to the clock delay control signal.

5. The integrated circuit device of claim 4, wherein the voltage controlled delay line comprises:

a plurality of series connected inverters arranged between an input receiving the clock signal and an output providing the delayed clock signal; and

a plurality of transistors having different threshold voltages, each transistor having a gate connected to a control voltage to operatively connect/disconnect a corresponding capacitor to an inverter in the plurality of inverters in response to the control voltage.

6. The integrated circuit device of claim 5, wherein the noise detector comprises:

a transistor connected as a source follower and configured to receive the power supply voltage and provide a source voltage;

a current source connected between the source voltage and ground;

a differential amplifier having a first terminal receiving the source voltage and a second terminal receiving a low-pass filtered version of the source voltage, and generating the clock delay control signal as the control voltage applied to the plurality of transistors in the voltage controlled delay line.

7. The integrated circuit device of claim 1, wherein the data transfer circuit is a plurality of data transfer circuits, each one of the plurality of data transfer circuits receiving respective input data and providing corresponding output data, each being powered by the power supply voltage, and each providing the corresponding output data synchronously with the delayed clock signal.

8. The integrated circuit device of claim 7, wherein the clock delay circuit is a plurality of clock delay circuits, each one of the plurality of clock delay circuits being operatively associated with one of the plurality of data transfer circuits to provide the one data transfer circuit with a respective delayed clock signal, such that the output data provided by each one of the plurality of data transfer circuits is provided synchronously with the respective delayed clock signal.

9. The integrated circuit device of claim 8, wherein each one of the plurality of clock delay circuits is a voltage controlled delay line receiving the clock signal and providing the respective delayed clock signal in response to the clock delay control signal.

10. The integrated circuit device of claim 1, wherein the clock delay circuit comprises a plurality of series connected voltage controlled delay lines receiving the clock signal and providing the delayed clock signal in response to the clock delay control signal.

11. The integrated circuit device of claim 10, wherein the data transfer circuit is a plurality of data transfer circuits, each one of the plurality of data transfer circuits receiving respective input data and providing corresponding output data, each being powered by the power supply voltage, and each providing the corresponding output data synchronously with the delayed clock signal.

12. The integrated circuit device of claim 11, wherein each one of the plurality of series connected voltage controlled delay lines provides a respective delayed clock signal to one of the plurality of the data transfer circuits, such that the output data provided by each one of the plurality of data transfer circuits is provided synchronously with the respective delayed clock signal.

13. The integrated circuit device of claim 1, wherein the power supply voltage noise component is a frequency component corresponding to variations in the frequency of noise associated with the power supply voltage.

14. The integrated circuit device of claim 1, wherein the noise detector comprises:

a power supply voltage amplitude noise detector configured to receive the power supply voltage and provide a first clock delay control signal corresponding to amplitude variation in the power supply voltage; and

a power supply voltage frequency noise detector configured to receive the power supply voltage and provide a second clock delay control signal corresponding to frequency variation of noise associated with the power supply voltage,

wherein the clock delay circuit is configured to receive the clock signal, and delay the clock signal in response to at least one of the first and second clock delay control signals to generate the delayed clock signal.

15. The integrated circuit device of claim 14, wherein the clock delay circuit comprises:

a first voltage controlled delay circuit configured to receive the clock signal and the first clock delay control signal, and provide a first delayed clock signal in response to the first power supply voltage signal, and

a second voltage controlled delay circuit configured to receive the first delayed clock signal and the second clock delay control signal, and provide a second delayed clock signal in response to the second power supply voltage signal, wherein the second delayed clock signal is the delay clock signal applied to the data transfer circuit.

16. The integrated circuit device of claim 15, wherein the clock delay circuit further comprises a controller turning the second voltage controlled delay line ON when the frequency variation of noise associated with the power supply voltage rises to a defined threshold.

17. A computational system comprising:

a processor connected via a system bus to a memory, wherein at least one of the processor and memory comprises a data input/output (I/O) interface connected to a data channel in the system bus,

the I/O interface comprising;

a noise detector circuit configured to receive a power supply voltage, detect a power supply voltage noise component from the power supply voltage, and provide a clock delay control signal in response to detected power supply voltage noise component;

a clock delay circuit configured to receive a clock signal, and delay the clock signal in response to the clock delay control signal to generate a delayed clock signal; and

a data transfer circuit configured to receive input data and provide output data corresponding to the input data, wherein the data transfer circuit is powered by the power supply voltage and provides the output data synchronously with the delayed clock signal.

18. The computational system of claim 17, wherein the power supply voltage noise component is at least one of an amplitude noise component corresponding to amplitude variations in the power supply voltage, and a frequency component corresponding to frequency variations in the power supply voltage.

19. The computational system of claim 17, wherein the clock delay circuit comprises at least one voltage controlled delay line.

20-35. -35. (canceled)

36. A memory device, comprising:

a memory cell array of memory cells configured to store write data and provide read data;

a noise detector circuit configured to receive a power supply voltage, detect a power supply voltage noise component from the power supply voltage, and provide a clock delay control signal in response to the detected power supply voltage noise component;

a clock delay circuit configured to receive a clock signal and delay the clock signal in response to the clock delay control signal to generate a delayed clock signal; and

a data transfer circuit configured to receive the read data from the memory cell array and provide output data corresponding to the read data, wherein the data transfer circuit is powered by the power supply voltage and provides the output data synchronously with the delayed clock signal.