Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines
First Claim
1. A data memory including memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having orthogonal x, y and z-directions and with a plurality of parallel planes stacked in the z-direction, the memory further comprising:
- a plurality of first conductive lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array in the x and y-directions,a plurality of second conductive lines elongated in the x-direction across individual planes and spaced apart in the y-direction between and separated from the first plurality of conductive lines in the individual planes, wherein the first and second conductive lines cross adjacent each other at a plurality of locations across the individual planes,a plurality of non-volatile re-programmable memory elements individually connected between the first and second conductive lines adjacent the crossings thereof at the plurality of locations, anda plurality of select devices arranged to individually connect selected ones of the plurality of first conductive lines to selected ones of a plurality of third conductive lines.
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Accused Products
Abstract
A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.
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Citations
49 Claims
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1. A data memory including memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having orthogonal x, y and z-directions and with a plurality of parallel planes stacked in the z-direction, the memory further comprising:
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a plurality of first conductive lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array in the x and y-directions, a plurality of second conductive lines elongated in the x-direction across individual planes and spaced apart in the y-direction between and separated from the first plurality of conductive lines in the individual planes, wherein the first and second conductive lines cross adjacent each other at a plurality of locations across the individual planes, a plurality of non-volatile re-programmable memory elements individually connected between the first and second conductive lines adjacent the crossings thereof at the plurality of locations, and a plurality of select devices arranged to individually connect selected ones of the plurality of first conductive lines to selected ones of a plurality of third conductive lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A re-programmable non-volatile semiconductor memory, comprising:
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a plurality of planes stacked on top of one another over a semiconductor substrate, in individual ones of the planes, a plurality of control gate lines elongated in a x-direction and spaced apart in a y-direction across the plane, a plurality of local bit lines extending from the substrate in a z-direction through the plurality of planes, arranged in a two-dimensional rectangular array in the x and y-directions and positioned through the individual planes between the control gate lines in the y-direction, the control gate and local bit lines therefore crossing adjacent each other at a plurality of locations in the plurality of planes, wherein the x, y and z-directions are orthogonal with each other as three-dimensional rectangular coordinates, a plurality of re-programmable non-volatile memory elements individually connected between the control gate and local bit lines adjacent the crossings thereof at the plurality of locations, individual memory elements having a detectable electrical characteristic that reversibly changes between at least two stable states in response to electrical stimuli applied thereto, and a plurality of select devices formed in the substrate to individually connect selected ones of the plurality of local bit lines to selected ones of a plurality of global bit lines formed in the substrate. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
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34. A method of operating a re-programmable non-volatile memory system, comprising:
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utilizing at least one integrated circuit that includes a three-dimensional pattern of memory elements defined by rectangular coordinates having orthogonal x, y and z-directions and which comprises; a plurality of parallel planes stacked in the z-direction on top of a semiconductor substrate, a plurality of conductive local bit lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array in the x and y-directions, a plurality of word lines elongated in the x-direction across individual planes and spaced apart in the y-direction between and separated from the plurality of local bit lines in the individual planes, wherein the local bit lines and word lines cross adjacent each other at a plurality of locations across the individual planes, a plurality of re-programmable non-volatile memory elements individually connected between the local bit lines and the word lines adjacent the crossings thereof at the plurality of locations, the memory elements being individually switchable between at least first and second stable electrically detectable states such that application of a first electrical stimuli thereto causes the memory element to switch from the first state to the second state and application of a second electrical stimuli thereto causes the memory element to switch from the second state to the first state, and a plurality of select devices formed in the substrate that individually connect selected ones of the plurality of local bit lines to selected ones of a plurality of global bit lines in response to select control signals, applying select control signals to the plurality of select devices in order to connect selected ones of the local bit lines to individual ones of the global bit lines, and causing a selected one or more of the plurality of memory elements to simultaneously change between their at least first and second states by applying one of the first and second stimuli through the word lines and global bit lines between which the selected one or more of the plurality of memory elements are operably connected. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41, 42)
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43. A method of forming a three-dimensional array of re-programmable non-volatile memory elements on a semi-conductor substrate, comprising:
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forming switching circuits in the semi-conductor substrate, thereafter forming a plurality of planes on top of each other and on top of the substrate, individual planes being formed by a dielectric layer with an electrically conductive layer thereover, forming a plurality of parallel trenches through the dielectric and conductive layers of the plurality of planes and to the substrate in a single etch operation, wherein the conductive layers of the planes are separated into first electrically conductive lines extending between the trenches and with-edges thereof making up portions of opposing sidewalls of the trenches, forming layers of non-conductive re-programmable non-volatile memory material continuously along opposing sidewalls of the trenches including in contact with the edges of the first conductive lines, and thereafter forming a plurality of second conductive lines within the trenches between and in contact with the opposing sidewall layers of memory material and spaced apart from each other along the trench, the second conductive lines additionally being formed to extend away from contact with the switching circuits in the substrate and continuously through the plurality of planes, wherein the three-dimensional array of re-programmable non-volatile memory elements is formed in portions of the layers of the memory material positioned between the edges of the first conductive lines and the second conductive lines. - View Dependent Claims (44, 45, 46)
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47. A method of forming a three-dimensional array of re-programmable non-volatile memory elements on a semi-conductor substrate, comprising:
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forming switching circuits in the semi-conductor substrate, forming a stack of a plurality of planes on top of the semiconductor substrate, the planes being individually formed in sequence by a method comprising; forming a first dielectric as a continuous bottom layer, forming a plurality of re-programmable non-volatile memory elements in a two-dimensional array across the dielectric layer, the array having rows and columns of discrete memory elements extending in respective first and second directions that are orthogonal with each other, and forming a first plurality of conductive lines having lengths extending in the first direction and being spaced apart in the second direction to overlay and form electrical contact with rows of memory elements, and after forming the stack of the plurality of planes, forming a second plurality of conductive lines that contact the switching circuits in the substrate and extend up through the plurality of planes, the second conductive lines being positioned between adjacent memory elements in the second direction in a manner to have an electrical connection therewith but remain insulated from the first conductive lines, wherein the three-dimensional array of re-programmable non-volatile memory elements is formed by the two-dimensional arrays of memory elements in the stack of the plurality of planes that are individually electrically connected between one of the first conductive lines and one of the second conductive lines. - View Dependent Claims (48, 49)
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Specification