Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines and a Double-Global-Bit-Line Architecture
First Claim
1. A data memory including memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes stacked in the z-direction, the memory further comprising:
- a plurality of first conductive lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of rows in the x-direction and columns in the y-direction;
a plurality of second conductive lines elongated in the x-direction across individual planes and spaced apart in the y-direction between and separated from the first plurality of conductive lines in the individual planes, wherein the first and second conductive lines cross adjacent each other at a plurality of locations across the individual planes;
a plurality of non-volatile re-programmable memory elements individually connected between the first and second conductive lines adjacent the crossings thereof at the plurality of locations; and
wherein;
a column of first conductive lines in the y-direction is switchably accessed by a corresponding third conductive line pair;
individual first conductive lines of even number in the column are switchably coupled to one line of the corresponding third conductive line pair; and
individual first conductive lines of odd number in the column are switchably coupled to another line of the corresponding third conductive line pair.
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Accused Products
Abstract
A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A double-global-bit-line architecture provides a pair of global bit lines for each bit lines for accessing a row of memory elements in parallel. A first one of each pair allows the local bit lines of the row to be sensed while a second one of each pair allows local bit lines in an adjacent row to be set to a definite voltage so as to eliminate leakage currents between adjacent rows of local bit lines.
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Citations
18 Claims
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1. A data memory including memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes stacked in the z-direction, the memory further comprising:
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a plurality of first conductive lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of rows in the x-direction and columns in the y-direction; a plurality of second conductive lines elongated in the x-direction across individual planes and spaced apart in the y-direction between and separated from the first plurality of conductive lines in the individual planes, wherein the first and second conductive lines cross adjacent each other at a plurality of locations across the individual planes; a plurality of non-volatile re-programmable memory elements individually connected between the first and second conductive lines adjacent the crossings thereof at the plurality of locations; and
wherein;a column of first conductive lines in the y-direction is switchably accessed by a corresponding third conductive line pair; individual first conductive lines of even number in the column are switchably coupled to one line of the corresponding third conductive line pair; and individual first conductive lines of odd number in the column are switchably coupled to another line of the corresponding third conductive line pair. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of operating a re-programmable non-volatile memory system, comprising:
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utilizing at least one integrated circuit that includes a three-dimensional pattern of memory elements defined by rectangular coordinates having x, y and z-directions and which comprises; a plurality of parallel planes stacked in the z-direction on top of a semiconductor substrate; a plurality of conductive local bit lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of rows in the x and columns in the y-directions; a plurality of word lines elongated in the x-direction across individual planes and spaced apart in the y-direction between and separated from the plurality of local bit lines in the individual planes, wherein the local bit lines and word lines cross adjacent each other at a plurality of locations across the individual planes; a plurality of re-programmable non-volatile memory elements individually connected between the local bit lines and the word lines adjacent the crossings thereof at the plurality of locations; and
wherein;a column of local bit lines in the y-direction is switchably accessed by a corresponding global bit line pair; individual local bit lines of even number in the column are switchably coupled to one designated line of the corresponding global bit line pair; and individual local bit lines of odd number in the column are switchably coupled to another designated line of the corresponding global bit line pair; a first plurality of select devices arranged to individually couple a selected row of local bit lines to a first designated lines of corresponding global bit line pairs in response to a select control signal; a second plurality of select devices arranged to individually couple an adjacent row of local bit lines to a second designated lines of corresponding global bit lines pairs in response to the select control signal; applying the select control signal to the first plurality of select devices in order to connect the selected row of local bit lines to the first designated lines of corresponding global bit line pairs; applying the select control signal to the second plurality of select devices in order to connect the adjacent row of local bit lines to the second designated lines of corresponding global bit line pairs; and causing a selected one or more of the plurality of memory elements to simultaneously change between their at least first and second states by applying one of the first and second stimuli through the word lines and global bit lines between which the selected one or more of the plurality of memory elements are operably connected. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification