Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines and a Single-Sided Word Line Architecture

• US 20100259962A1
• Filed: 03/26/2010
• Published: 10/14/2010
• Est. Priority Date: 04/08/2009
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Yan, Tianhong, Samachisa, George
• Granted Patent: US 8,351,236 B2
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 11/06035 Bit core selection for writing or reading, by at least two coincident partial currents, e.g. "bit"- organised, 2L/2D, or 3D
• CPC Class Codes: G11C 11/5614 using conductive bridging RAM [CBRAM] or programming metallization cells [PMC]
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2013/0045 Read using current through the cell
• CPC Class Codes: G11C 2013/0088 Write with the simultaneous writing of a plurality of cells
• CPC Class Codes: G11C 2213/19 Memory cell comprising at least a nanowire and only two terminals
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/34 Material includes an oxide or a nitride
• CPC Class Codes: G11C 2213/55 Structure including two electrodes, a memory active layer and at least two other layers which can be a passive or source or reservoir layer or a less doped memory active layer
• CPC Class Codes: G11C 2213/71 : Three dimensional array
• CPC Class Codes: G11C 2213/75 : Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
• CPC Class Codes: G11C 2213/78 : Array wherein the memory cells of a group share an access device, all the memory cells of the group having a common electrode and the access device being not part of a word line or a bit line driver
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H10B 63/20 : comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/84 : arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10B 63/845 : the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/231 : based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/235 : between different crystalline phases, e.g. cubic and hexagonal
• CPC Class Codes: H10N 70/24 : based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/245 : the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/826 : adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/841 : Electrodes
• CPC Class Codes: H10N 70/8416 : adapted for supplying ionic species
• CPC Class Codes: H10N 70/8822 : Sulfides, e.g. CuS
• CPC Class Codes: H10N 70/8825 : Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/884 : Other compounds of groups 13-15, e.g. elemental or compound semiconductors
• CPC Class Codes: H10N 70/8845 : Carbon or carbides

Abstract

A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line.

Claims

1. A data memory including memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes stacked in the z-direction, the memory further comprising:

a plurality of first conductive lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of rows in the x-direction and columns in the y-direction;

a plurality of second conductive lines elongated in the x-direction across individual planes and spaced apart in the y-direction between and separated from the first plurality of conductive lines in the individual planes, wherein the first and second conductive lines cross adjacent each other at a plurality of locations across the individual planes;

each adjacent pair of the second conductive lines being disposed around a corresponding row of first conductive lines in the x-direction for operating exclusively therewith;

a plurality of non-volatile re-programmable memory elements individually connected between the first conductive lines and second conductive lines adjacent the crossings thereof at the plurality of locations; and

a plurality of select devices arranged to individually couple a selected row of first conductive lines to a plurality of third conductive lines.

2. The memory of claim 1, wherein

the third conductive lines are elongated in the y-direction,

the select devices are arranged to make those of the first conductive lines aligned in the y-direction connectable with selected ones of the plurality of third conductive lines, and

a plurality of control lines extending in the x-direction and individually connected with a plurality of the select devices aligned in the x-direction to enable connection of a plurality of first conductive lines aligned in the x-direction with different ones of the third conductive lines.

3. The memory of either one of claim 1 or 2, wherein the plurality of select devices and the plurality of third conductive lines are formed in a semiconductor substrate and the plurality of planes are formed as a stack over the semiconductor substrate.

4. The memory of any one of claims 1 and 3, wherein the individual memory elements are characterized by including a material that reversibly changes its level of electrical conductance between at least first and second stable levels in response to an electrical stimulus being applied through the first and second conductive lines between which the memory element is connected.

5. The memory of claim 1, wherein memory elements include individual quantities of material adjacent individual ones of the crossings of the first and second conductive lines, the memory elements being separated from one another in all of the x, y and z-directions.

6. The memory of claim 1, wherein the memory elements are additionally positioned to contact the first conductive lines in the y-direction.

7. The memory of claim 1, wherein the individual memory elements are characterized by a level of electrical conductance that changes in response to an electrical stimulus applied thereto.

8. The memory of claim 1, wherein the memory elements are characterized by having at least first and second stable electrically detectable states that are selected by electrical stimuli applied thereto through the first and second conductive lines.

9. The memory of claim 1, additionally comprising a circuit connected to the first and second conductive lines to apply the electrical stimuli to selected ones of the memory elements, the electrical stimuli being applied to cause the selected memory elements to switch from their first to second stable states having substantially the same magnitude but different polarities as the electrical stimuli applied to cause the memory elements to switch from their second to first stable states.

10. The memory of claim 1, additionally comprising data input-output circuits connected to the third plurality of conductive lines.

11. The memory of claim 10, wherein the data input-output circuits include a plurality of sense amplifiers that are connected with the third conductive lines in a manner to provide a binary representation of data carried by the third conductive lines when data are being read from the memory.

12. The memory of claim 10, wherein the data input-output circuits additionally include data programming circuits that apply voltages to the selected ones of the third conductive lines for programming data into at least some of the memory elements connected thereto through the plurality of select devices.

13. A method of operating a re-programmable non-volatile memory system, comprising:

utilizing at least one integrated circuit that includes a three-dimensional pattern of memory elements defined by rectangular coordinates having x, y and z-directions and which comprises;

a plurality of parallel planes stacked in the z-direction on top of a semiconductor substrate;

a plurality of conductive local bit lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of rows in the x and columns in the y-directions;

a plurality of word lines elongated in the x-direction across individual planes and spaced apart in the y-direction between and separated from the plurality of local bit lines in the individual planes, wherein the local bit lines and word lines cross adjacent each other at a plurality of locations across the individual planes;

each adjacent pair of word lines of the plurality of word lines being disposed around a corresponding row of local bit lines in the x-direction for operating exclusively therewith;

a plurality of re-programmable non-volatile memory elements individually connected between the local bit lines and the word lines adjacent the crossings thereof at the plurality of locations; and

a plurality of select devices arranged to individually couple a selected row of local bit lines to a plurality of global bit lines in response to select control signals;

applying select control signals to the plurality of select devices in order to connect selected row of local bit lines to individual ones of the global bit lines, and

causing a selected one or more of the plurality of memory elements to simultaneously change between their at least first and second states by applying one of the first and second stimuli through the word lines and global bit lines between which the selected one or more of the plurality of memory elements are operably connected.

14. The method of claim 13, wherein applying select control signals includes applying the select control signals to the plurality of select devices in order to connect a row of the local bit lines extending in the x-direction to the global bit lines.

15. The method of claim 14, wherein causing a selected one or more of the plurality of memory elements to simultaneously change between their at least first and second states includes simultaneously resetting to the first state two rows of memory elements connected to the selected row of local bit lines and along opposite sides thereof in the y-direction by applying the second electrical stimulus to a plurality of the global bit lines and to two of the word lines adjacent the selected row of local bit lines on said opposite sides thereof.

16. The method of claim 14, wherein causing a selected one or more of the plurality of memory elements to simultaneously change between their at least first and second states additionally includes subsequently programming data into one of the two rows of reset memory elements by applying the first electrical stimulus to a plurality of the global bit lines and one of the word lines adjacent the selected row of local bit lines on the side thereof of the one row of memory elements being programmed.

17. The method of claim 14, additionally comprising reading the states of a row of memory elements along one side in the y-direction of the selected row of local bit lines by applying reading electrical stimuli to the global bit lines and word lines such that the states of the memory elements are read from an electrical quantity appearing on the global bit lines.

18. The method of claim 14, wherein causing a selected one or more of the plurality of memory elements to simultaneously change between their at least first and second states additionally includes applying a plurality of pulses of the one of the first and second stimuli and, in between successive pulses, verifying the state of the one or more of the plurality of memory elements.