NONVOLATILE MEMORY DEVICE AND DATA RANDOMIZING METHOD THEREOF

• US 20100259983A1
• Filed: 04/01/2010
• Published: 10/14/2010
• Est. Priority Date: 04/08/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yoon, Sangyong
• Granted Patent: US 8,339,854 B2
• Time in Patent Office: Days
• US Class Current: 365/185.120
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A method is for operating a nonvolatile memory device, where the memory device includes a memory cell array and a page buffer block. The method includes loading program data into the page buffer block, loading random sequence data into the page buffer block, generating randomized data by executing a logic operation, such as a bit-wise XOR operation, in the page buffer circuit on the program data and the first random sequence data, and programming the randomized data into the memory cell array.

Claims

1. A method of operating a nonvolatile memory device including a memory cell array and a page buffer block, the method comprising:

loading program data into the page buffer block;

loading random sequence data into the page buffer block;

generating randomized data by executing a logic operation in the page buffer circuit on the program data and the first random sequence data; and

programming the randomized data into the memory cell array.

2. The method of claim 1, wherein the random sequence data is generated using an address of the program data as a seed value.

3. The method of claim 1, wherein the logic operation is a bit-wise XOR operation.

4. The method of claim 1, wherein the random sequence data is first random sequence data, and further comprising:

sensing data during a sensing period from the memory cell array;

loading second random sequence data during the sensing period into the page buffer block;

generating de-randomized data by executing the logic operation in the page buffer circuit on the sensed data and the second random sequence data; and

outputting the de-randomized data.

5. The method of claim 4, wherein the second random sequence data is generated using an address associated with the sensed data as a seed value.

6. The method of claim 4, wherein the logic operation is a bit-wise XOR operation.

7. The method of claim 4, wherein the program data is random data received during a copy-back program operation.

8. The method of claim 1, wherein the nonvolatile memory device is a flash memory device.

9. A nonvolatile memory device, comprising:

a memory cell array storing data information;

a random sequence generator configured to generate random sequence data;

a page buffer block configured to latch data to be programmed to the memory cell array; and

a control logic configured to control the random sequence generator and the page buffer block,

wherein the control logic controls the random sequence generator and the page buffer block such that the random sequence data is loaded into the page buffer circuit after the data to be programmed is loaded into the page buffer circuit, and wherein the control logic controls the page buffer circuit to perform a logic operation in which the loaded data is randomized based on the loaded random sequence data.

10. The nonvolatile memory device of claim 9, wherein the page buffer circuit is further for sensing data from the memory cell array, the control logic controls the page buffer circuit and the random sequence generator such that the random sequence data is loaded into the page buffer circuit during the sensing of data by the page buffer circuit.

11. The nonvolatile memory device of claim 10, wherein the control logic controls the page buffer circuit to perform the logic operation in which the sensed data is de-randomized based on the loaded random sequence data.

12. The nonvolatile memory device of claim 11, wherein the logic operation is a bit-wise XOR operation.

13. The nonvolatile memory device of claim 9, wherein the logic operation is a bit-wise XOR operation.

14. The nonvolatile memory device of claim 9, further comprising:

a multiplexer configured to selectively send the data to be programmed or the random sequence data to the page buffer circuit in response to a control of the control logic.

15. The nonvolatile memory device of claim 11, wherein the page buffer circuit comprises a plurality of page buffers, each of the plurality of page buffers including a first latch for storing the data to be programmed and a second latch for storing the random sequence data, and wherein data randomized and de-randomized by the logic operation is stored in the first latch or a third latch.

16. The nonvolatile memory device of claim 9, wherein the memory cell array is a flash memory cell array.

17. A program method of a nonvolatile memory device including a memory cell array and a page buffer block, the method comprising:

loading program data into the page buffer block;

loading random sequence data into the page buffer block;

generating randomized data by executing a logic operation in the page buffer circuit on the program data and the first random sequence data; and

programming the randomized data into the memory cell array,

wherein the random sequence data is loaded into the page buffer block before or after the program data is loaded into the page buffer block.

18. The method of claim 17, wherein the random sequence data is 1-bit data.

19. The method of claim 18, wherein the logic operation is a bit-wise XOR operation.

20. The method of claim 17, wherein the nonvolatile memory device is a flash memory device.