Nanostructures, methods of depositing nanostructures and devices incorporating the same

• US 20100261338A1
• Filed: 12/04/2006
• Published: 10/14/2010
• Est. Priority Date: 12/04/2006
• Status: Active Grant

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Balch, Joleyn Eileen, Tsakalakos, Loucas
• Granted Patent: US 8,258,047 B2
• Time in Patent Office: Days
• US Class Current: 438/478
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 21/02628 using solutions
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method for depositing nanowires is disclosed. The method includes depositing multiple nanowires onto a surface of a liquid. The method also includes partially compressing the nanowires. The method also includes dipping a substrate into the liquid. The method further includes pulling the substrate out of the liquid at a controlled speed. The method also includes transferring the nanowires onto the substrate parallel to a direction of the pulling.

Claims

1. A method for depositing nanowires comprising:

depositing a plurality of nanowires onto a surface of a liquid;

partially compressing the plurality of nanowires;

dipping a substrate into the liquid;

pulling the substrate out of the liquid at a controlled speed; and

transferring the plurality of nanowires onto the substrate parallel to a direction of the pulling.

2. The method of claim 1, wherein partially compressing comprises depositing a plurality of spacer molecules between the nanowires.

3. The method of claim 1, wherein dipping a substrate comprises dipping via a plurality of rollers.

4. The method of claim 1, wherein pulling the substrate out comprises pulling out via a plurality of rollers.

5. The method of claim 1, wherein the controlled speed comprises a range between about 5 mm/min and 300 mm/min.

6. The method of claim 1, further comprising applying a plurality of magnetic electrodes on the substrate and applying magnetic tips on the plurality of nanowires.

7. The method of claim 1, further comprising chemically treating the substrate in order to control placement of the plurality of nanowires in pre-defined locations.

8. The method of claim 1, wherein transferring further comprises generating standing waves in the liquid in order to trap the plurality of nanowires.

9. The method of claim 1, wherein the liquid comprises deionized water.

10. An electronic device comprising a plurality of nanowires disposed on a substrate and aligned in a single direction on the substrate within a range of about +/−

20 degrees and having a density ranging between about 5 percent and about 90 percent of an area of deposition of the plurality of nanowires on the substrate.

11. The electronic device of claim 10, wherein the electronic device comprises a nanowire field effect transistor and wherein the plurality of nanowires are aligned in a direction from a source to a drain of the nanowire field effect transistor.

12. The electronic device of claim 10, further comprising a dielectric layer between the substrate and the nanowires.

13. The electronic device of claim 12, wherein the dielectric layer comprises silicon dioxide, silicon nitride, aluminum oxide, zirconium oxide, and hafnium oxide.

14. The electronic device of claim 10, wherein the substrate comprises a flexible substrate.

15. The electronic device of claim 10, wherein the substrate comprises silicon, a metal, a polymer, and glass, or a combination thereof.

16. The electronic device of claim 10, wherein the substrate comprises a chemically treated substrate.

17. The electronic device of claim 16, wherein the chemically treated substrate comprises 3-aminopropyltriethoxysilane.

18. The electronic device of claim 10, wherein the plurality of nanowires comprises a conductive material and a semiconductive material.

19. The electronic device of claim 18, wherein the conductive material comprises one of gold, nickel, palladium, cobalt, chromium, or conductive polymers or a combination thereof.

20. The electronic device of claim 18, wherein the semiconductive material comprises one of silicon, germanium, silicon-germanium, silicon carbide, indium oxide, tin oxide, selenium, bismuth-tellerium, boron, carbon, gallium nitride, indium-gallium-nitride, aluminum-gallium-nitride, zinc oxide, cadmium-selenium, cadmium-tellurium, gallium arsenide, aluminum arsenide, gallium phosphide, indium phosphide, indium antimonide, gallium antimonide, and transition metal carbides or a combination thereof.

21. A method of fabricating a nanoelectronic device array comprising:

depositing a plurality of nanowires onto a surface of a liquid;

partially compressing the plurality of nanowires;

dipping a substrate into the liquid;

pulling the substrate out of the liquid at a controlled speed;

transferring the plurality of nanowires onto the substrate parallel to a direction of the pulling;

forming a source electrode on the plurality of nanowires;

forming a drain electrode on the plurality of nanowires; and

forming a gate electrode.

22. The method of claim 21, further comprising depositing a gate dielectric on the gate electrode.

23. The method of claim 21, further comprising depositing a gate dielectric on the plurality of nanowires.

24. The method of claim 21, wherein forming the source electrode, drain electrode and gate electrode comprises employing photolithographic techniques.

25. The method of claim 21, further comprises chemically treating the substrate in selective areas before dipping the substrate into the liquid.

26. The method of claim 25, wherein chemically treating comprises chemically treating portions of the substrate with a hydrophobic material.

27. The method of claim 21, wherein dipping a substrate comprises dipping via a plurality of rollers.

28. The method of claim 21, wherein pulling the substrate out comprises pulling out via a plurality of rollers.

29. The method of claim 21, wherein transferring further comprises generating standing waves in the liquid in order to trap the plurality of nanowires.

30. The method of claim 21, further comprising fabricating a nano field effect transistor array, a nano p-n junction device array, a nanoelectronic logic circuit array, a nanoscale chemical, physical, or biological sensor array, a nanoelectromechanical device array, or a photodetector array.

31. A system for depositing nanowires comprising:

a trough configured to contain a liquid;

a plurality of rollers configured to move a flexible substrate through the trough containing the liquid;

a nanowire dispensing unit configured to deposit a plurality of nanowires onto a surface of the liquid; and

a barrier configured to compress the plurality of nanowires.

32. The system of claim 31, further comprising a control system configured to automate motion of the plurality of rollers.