MEMORY CONTROLLERS, MEMORY SYSTEMS, SOLID STATE DRIVES AND METHODS FOR PROCESSING A NUMBER OF COMMANDS

• US 20100262721A1
• Filed: 04/09/2009
• Published: 10/14/2010
• Est. Priority Date: 04/09/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Asnaashari, Mehdi, Nemazie, Siamack, Liao, Yu-Song, Yang, Jui-Yao ("Ray")
• Granted Patent: US 8,055,816 B2
• Time in Patent Office: Days
• US Class Current: 710/5
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Claims

1. A memory controller, comprising:

a plurality of back end channels;

a command queue communicatively coupled to the plurality of back end channels, the command queue being configured to hold host commands communicated by a host; and

circuitry configured to;

generate a number of back end commands at least in response to a number of the host commands in the command queue, and

distribute the number of back end commands to a number of the plurality of back end channels.

2. The memory controller of claim 1, wherein the number of back end commands is fewer than the number of the host commands.

3. The memory controller of claim 1, wherein the number of back end commands is greater than the number of the host commands.

4. The memory controller of claim 3, wherein the circuitry is configured to:

generate a respective back end command corresponding to each of the plurality of back end channels in response to a single host command, and

distribute the respective back end command to its corresponding back end channel, such that the back end commands are processed substantially in parallel.

5. The memory controller of claim 4, wherein the circuitry is configured to communicate results to the host from executing a particular one of the multiple back end commands upon completion of the particular one of the multiple back end commands, without regard to completion of execution of any other of the multiple back end commands.

6. The memory controller of claim 1, wherein the circuitry is configured to distribute multiple host commands among different multiple back end channels such that the multiple host commands are executed substantially simultaneously.

7. The memory controller of claim 1, wherein generating the number of back end commands includes the combination of modifying at least one of the number of host commands and deleting at least another one of the number of host commands.

8. The memory controller of claim 1, wherein a Direct Memory Access module (DMA) is configured to distribute data associated with a host command corresponding to the number of back end commands generated.

9. The memory controller of claim 1, wherein the circuitry is a command dispatcher having a command processor portion configured to modify host commands so as to optimize distribution of the commands among the plurality of back end channels, and a dispatcher portion configured to distribute the modified commands among the plurality of back end channels.

10. The memory controller of claim 1, wherein the circuitry is a front end processor (FEP) communicatively coupled to the plurality of back end channels, the FEP being configured to modify host commands so as to optimize distribution of the commands among the plurality of back end channels.

11. A memory controller, comprising:

a plurality of back end channels; and

a front end command dispatcher communicatively coupled to the plurality of back end channels and a command queue configured to hold a number of read commands,

wherein the command dispatcher is configured to determine a net read from memory to be accomplished by the number of read commands, and to modify one or more of the number of read commands in order to optimize distribution of the number of read commands among the plurality of back end channels.

12. The memory controller of claim 11, wherein the front end command dispatcher includes a command processor portion configured to modify one or more commands so as to optimize distribution of the commands among the plurality of back end channels, and a dispatcher portion configured to distribute commands among the plurality of back end channels.

13. The memory controller of claim 11, wherein the front end command dispatcher is configured to perform host command integrity checking in hardware.

14. The memory controller of claim 11, including a front end processor (FEP) communicatively coupled to the plurality of back end channels,

wherein the FEP is configured to determine a net read from memory to be accomplished by the number of read commands, and to modify one or more of the number of read commands in order to optimize distribution of the number of read commands among the plurality of back end channels.

15. A memory controller, comprising:

a plurality of back end channels; and

a front end command dispatcher communicatively coupled to the plurality of back end channels and a command queue configured to hold a number of write commands,

wherein the command dispatcher is configured to determine a net change to memory to be accomplished by the number of write commands, and to modify one or more of the number of write commands in order to optimize distribution of the number of write commands among the plurality of back end channels.

16. The memory controller of claim 15, wherein the command dispatcher is configured to modify the one or more of the number of write commands in order to optimize distribution only when the plurality of back end channels are busy.

17. The memory controller of claim 15, wherein the command dispatcher is configured to not distribute one of the number of write commands from the command queue without changing the determined net change to memory by the number of write commands.

18. The memory controller of claim 17, wherein the command dispatcher is configured to modify a memory range associated with a first write command in the command queue to include a portion of the memory range of a second write command in the command queue, and thereafter not distribute the second write command from the command queue without changing the determined net change to memory by the number of write commands.

19. The memory controller of claim 15, wherein the number of write commands are received in the command queue in an initial order, and the command dispatcher is configured to change an order of the number of write commands in the command queue from the initial order to a changed order.

20. The memory controller of claim 19, wherein the command dispatcher is configured to distribute commands according to the changed order of the number of write commands in the command queue rather than according to the initial order.

21. The memory controller of claim 15, wherein the command dispatcher is configured to modify at least one of the number of write commands in the command queue by combining commands to overlapping memory locations.

22. The memory controller of claim 21, wherein the command dispatcher is configured to change an order of the number of write commands in the command queue to a changed order in response to at least one of the number of write commands being modified.

23. The memory controller of claim 21, wherein the command dispatcher is configured to not distribute a write command determined to involve a number of memory locations that will be overwritten by a write command to be subsequently-executed in the command queue.

24. The memory controller of claim 21, wherein the command dispatcher is configured to not execute a write command determined to involve the number of memory locations that will be overwritten by a subsequently-executed write command without an intervening read operation involving the number of memory locations.

25. The memory controller of claim 21, wherein the command dispatcher is configured to group multiple write commands into a single write command.

26. The memory controller of claim 25, wherein the command dispatcher is configured to determine that at least two write commands are a same operation involving logically adjacent memory locations, and combine the at least two write commands into a single write command involving the logically adjacent memory locations.

27. The memory controller of claim 25, wherein the command dispatcher is configured to determine that at least two write commands are a same operation involving logically overlapping memory locations, and combine the at least two write commands into a single write command involving the logically overlapping memory locations.

28. The memory controller of claim 15, wherein the payload associated with a particular write command is distributed among more than one of the plurality of back end channels, and the command dispatcher is configured to distribute the particular write command to each of the more than one of the plurality of back end channels.

29. The memory controller of claim 28, wherein the command dispatcher is configured to determine an associated logical block address and sector count for a portion of the payload associated with each of the more than one of the plurality of back end channels, and modify the particular write command distributed to a respective back end channel with the logical block address and sector count for the associated portion of the payload.

30. The memory controller of claim 15, wherein the command dispatcher is configured to modify write commands in the command queue during a time when the command dispatcher is prevented from distributing commands to the plurality of back end channels.

31. A memory system, comprising:

a number of memory devices; and

a controller having a front end direct memory access module (DMA) and a number of back end channels communicatively coupled between a respective one of the number of memory devices and the front end DMA;

the front end DMA being configured to process a payload associated with a single host command communicated by the host, wherein respective portions of the payload are associated with corresponding multiple back end commands that are being substantially simultaneously executed across the number of back end channels.

32. The memory system of claim 31, wherein the single host command is a write command, and the front end DMA is configured to distribute the payload associated with the single host command amongst more than one of the number of back end channels corresponding to the multiple back end commands.

33. The memory system of claim 31, wherein the single host command is a read command, and the front end DMA is configured to assemble a payload associated with the single host command from amongst more than one of the number of back end channels corresponding to the multiple back end commands.

34. The memory system of claim 31, wherein the front end DMA is configured to determine a logical block address and sector count for each respective portion of the payload associated with each of the multiple back end commands, wherein each of the multiple back end commands mimic the host command but with a modified respective logical block address and sector count corresponding to a respective one of the number of back end channels.

35. The memory system of claim 31, wherein the front end DMA is configured to communicate portions of the payload associated with the multiple back end commands to a host in an order different than an order in which the host command would have produced the payload if it had been executed by a single back end channel.

36. The memory system of claim 35, wherein the front end DMA is configured to communicate portions of the payload associated with the multiple back end commands in an order in which the portions are received from the plurality of back end channels.

37. The memory system of claim 31, wherein the front end DMA is configured to communicate indicators of command completion status to the host in an order different than an order in which host commands are communicated by the host.

38. The memory system of claim 37, wherein the front end DMA is configured to communicate an indicator of command completion status to the host in an order in which back end commands are completed by the number of back end channels.

39. The memory system of claim 31, wherein each of the portions corresponds to a particular back end channel, and wherein the front end DMA is configured to communicate each of the portions individually to the host separate from the other portions.

40. The memory system of claim 39, wherein the front end DMA is configured to communicate one of the portions to the host upon receipt of the respective portion from one of the number of back end channels, and without assembling the portions into a complete payload associated with the single host command.

41. The memory system of claim 40, wherein the single host command is a read command and each of the portions is associated with a different back end channel.

42. The memory system of claim 40, wherein the front end DMA is configured to communicate each of the portions to the host as one of the number of back end channels completes processing the portion associated therewith.

43. The memory system of claim 31, wherein the single host command is a write command received at the front end DMA as part of a first order of host commands, the host commands being completed in a second order, and the front end DMA is configured to communicate an indicator of a command completion status of the single host command to the host according to the second order.

44. A solid state drive, comprising:

a plurality of flash memory devices;

a memory controller, comprising;

a plurality of back end channels, each communicatively coupled to a number of the plurality of memory devices;

a front end direct memory access (DMA) communicatively coupled to the plurality of back end channels;

a front end command dispatcher communicatively coupled to the DMA having a command queue configured to hold a number of commands;

wherein the command dispatcher is configured to process commands to optimize their distribution among the plurality of back end channels based on the number of commands then held in the command queue, and the front end DMA is configured to process respective payload associated with at least one command that involves more than one of the plurality of back end channels.

45. The solid state drive of claim 44, including a Serial Advanced Technology Attachment (SATA) interface communicatively coupled to the memory controller, the SATA interface being configured to communicate with a host.

46. The solid state drive of claim 44, wherein each of the plurality of back end channels is communicatively coupled to a respective one of the plurality of memory devices.

47. The solid state drive of claim 46, wherein the plurality of flash memory devices comprises eight NAND flash memory devices, and wherein the plurality of back end channels comprises eight back end channels.

48. The solid state drive of claim 44, wherein the command dispatcher is configured to process commands on a front end of the controller to optimize their distribution to a back end of the controller by selectively re-ordering commands, selectively combining commands, and/or selectively deleting commands.

49. The solid state drive of claim 48, wherein each of the plurality of back end channels is configured to further process respectively-received commands to expedite the execution of the respectively-received commands by selectively re-ordering received commands, selectively combining received commands, and/or selectively deleting commands.

50. A method of processing a number of commands before distributing the number of commands among a plurality of back end channels, comprising:

receiving a number of commands from a host in an order;

processing the number of commands to improve front end throughput, the processing comprising;

re-ordering the commands;

combining multiple commands into a single command; and

/or

deleting a command that involves a memory location determined to be overwritten by a subsequently-executed command without an intervening operation involving the memory location,

wherein at least one of the number of commands is distributed to more than one back end channel.

51. The method of claim 50, wherein the processing occurs only when the back end channels are busy.

52. The method of claim 50, wherein the re-ordering is in response, at least in part, to combining commands or deleting commands.

53. The method of claim 50, wherein combining multiple commands includes grouping commands involving adjacent memory locations into a single command.

54. The method of claim 50, wherein combining multiple commands includes grouping commands involving the number of same memory locations into a single command.

55. The method of claim 50, wherein combining commands includes coalescing commands involving sequential memory locations on a particular memory device into a single command.

56. The method of claim 50, wherein combining commands includes coalescing commands involving overlapping memory locations on a particular memory device into a single command.

57. The method of claim 50, wherein the processing includes determining for the at least one of the number of commands, a respective logical block address and sector count for each portion of a payload associated with the at least one of the number of commands and modifying the at least one of the number of commands distributed to the particular back end channel with the respective logical block address and sector count.

58. A method of processing a number of commands, comprising:

receiving a number of commands from a host in an order;

processing at least one command associated with payload involving more than one of the plurality of back end channels.

59. The method of claim 58, including distributing the payload associated with the at least one command amongst more than one of the plurality of back end channels wherein the at least one command is a write command.

60. The method of claim 58, including assembling the payload associated with the at least one command from more than one of the plurality of back end channels wherein the at least one command is a read command.

61. The method of claim 58, including:

determining an associated logical block address and sector count for each portion of the payload involving a respective one of the plurality of back end channels associated with the at least one command; and

modifying the at least one command distributed to the respective back end channel with the determined logical block address and sector count particular to the respective back end channel.

62. The method of claim 58, including:

receiving payload associated with one of the number of commands from the back end channels; and

communicating to the host the received payload in accordance with an order that is different from the order in which the number of commands were communicated by the host.

63. The method of claim 58, including communicating to the host, a portion of the payload received from one of the back end channels without waiting to receive another portion of the payload from another one of the backend channels.

64. The method of claim 63, including communicating to the host, the portion of the payload received from the one of the back end channels without re-assembling the payload.

65. The method of claim 58, including communicating an indicator of a completion status of a particular command of the number of commands, to the host, at completion of the particular command and independent of the order in which the commands were communicated by the host.

66. The method of claim 65, including:

receiving a first command before receiving the particular command;

distributing the first command to a first back end channel;

distributing the particular command to a second back end channel; and

communicating the indicator of the completion status of the particular command to the host upon completion of the particular command and regardless of completion of the first command.

67. The method of claim 58, including processing the number of commands to improve front end throughput before distributing the number of commands among the plurality of back end channels, the command processing including one or more of:

re-ordering the commands;

combining multiple commands; and

/or deleting commands.

68. The method of claim 67, including distributing the payload associated with at least one combined command amongst more than one of the plurality of back end channels, wherein commands being combined have at least a portion of their payload involved with a particular one of the plurality of back end channels.