MULTIPLE COMMAND QUEUES HAVING SEPARATE INTERRUPTS

• US 20100262740A1
• Filed: 08/07/2009
• Published: 10/14/2010
• Est. Priority Date: 04/08/2009
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Sprinkle, Robert S., Grundler, Grant, Borchers, Albert T., Swing, Andrew T.
• Granted Patent: US 8,380,909 B2
• Time in Patent Office: Days
• US Class Current: 710/263
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A host device may include a driver that is arranged and configured to communicate commands to a data storage device and multiple pairs of queues, where each of the pairs of queues may include a command queue that is populated with commands for retrieval by the data storage device and a response queue that is populated with responses by the data storage device for retrieval by the host device, where each response queue is associated with an interrupt and an interrupt handler.

Claims

1. A host device, comprising:

a driver that is arranged and configured to communicate commands to a data storage device; and

multiple pairs of queues, wherein each of the pairs of queues comprises;

a command queue that is populated with commands for retrieval by the data storage device, and

a response queue that is populated with responses by the data storage device for retrieval by the host device, wherein each response queue is associated with an interrupt and an interrupt handler.

2. The host device of claim 1 wherein an instance of the driver is configured to operate with each of the pairs of queues.

3. The host device of claim 1 further comprising:

an application that is configured to generate input and output requests; and

an operating system that is operably coupled to the driver and to the application and that is configured to communicate the input and output requests between the application and the driver.

4. The host device of claim 3 wherein the application comprises an application command queue and an application response queue to enable the application to communicate directly with the data storage device.

5. The host device of claim 3 wherein the application comprises an application command queue and an application response queue to enable the application to bypass the operating system and the driver.

6. The host device of claim 3 wherein the application comprises an application command queue and an application response queue to enable the application to communicate read requests directly to the data storage device and to receive responses to the read requests directly from the data storage device.

7. The host device of claim 6 wherein the application is configured to communicate write requests using the operating system and the driver.

8. The host device of claim 1 further comprising multiple applications that are configured to generate input and output requests, wherein each of the applications comprises an application command queue and an application response queue to enable each of the applications to communicate directly with the data storage device.

9. The host device of claim 1 wherein the interrupt handler for each of the response queues is configured to receive an interrupt from the data storage device designated for a specific response queue.

10. A method for communicating commands between a host and a data storage device, the method comprising:

using multiple different threads to communicate commands to a data storage device;

using multiple pairs of queues, wherein each pair of queues includes a command queue, a response queue, an interrupt and an interrupt handler; and

associating each pair of the queues with one or more of the threads, wherein using the pairs of queues comprises;

populating the command queue with commands for retrieval by the data storage device, and

populating the response queue with responses by the data storage device for retrieval by a host device.

11. The method as in claim 10 wherein using the multiple pairs of queues comprises operating an instance of a driver with each of the pairs of queues.

12. The method as in claim 10 further comprising using an application to communicate input and output requests directly with the data storage device, wherein using the application comprises:

populating an application command queue by the application with commands for retrieval by the data storage device, and

populating an application response queue by the data storage device with responses for retrieval by the application.

13. The method as in claim 12 wherein using the application comprises bypassing a driver on the host and an operating system on the host to communicate directly with the data storage device.

14. A system comprising:

a data storage device including a plurality of memory chips and multiple physical channels for communication of data between a host and the plurality of memory chips, each channel being operably connected to a different plurality of the memory chips; and

a host operably coupled to the data storage device using an interface, the host comprising;

a driver that is arranged and configured to communicate commands to the data storage device; and

multiple pairs of queues, wherein each of the pairs of queues comprises;

a command queue that is populated with commands for retrieval by the data storage device, and

a response queue that is populated with responses by the data storage device for retrieval by the host device, wherein each response queue is associated with an interrupt and an interrupt handler.

15. The system of claim 14 wherein an instance of the driver is configured to operate with each of the pairs of queues.

16. The system of claim 14 further comprising:

an application that is configured to generate input and output requests; and

an operating system that is operably coupled to the driver and to the application and that is configured to communicate the input and output requests between the application and the driver.

17. The system of claim 16 wherein the application comprises an application command queue and an application response queue to enable the application to communicate directly with the data storage device.

18. The system of claim 16 wherein the application comprises an application command queue and an application response queue to enable the application to bypass the operating system and the driver.

19. The system of claim 16 wherein the application comprises an application command queue and an application response queue to enable the application to communicate read requests directly to the data storage device and to receive responses to the read requests directly from the data storage device.

20. The system of claim 19 wherein the application is configured to communicate write requests using the operating system and the driver.

21. The system of claim 14 further comprising multiple applications that are configured to generate input and output requests, wherein each of the applications comprises an application command queue and an application response queue to enable each of the applications to communicate directly with the data storage device.

22. The system of claim 14 wherein the interrupt handler for each of the response queues is configured to receive an interrupt from the data storage device designated for a specific response queue.

23. The system of claim 14 wherein the plurality of memory chips comprise flash memory chips.

24. The system of claim 14 wherein the plurality of memory chips comprise dynamic random access memory (DRAM) chips.

25. The system of claim 14 wherein the plurality of memory chips comprise phase change memory (PCM) chips.