Communication Processor Board

• US 20100262749A1
• Filed: 07/25/2005
• Published: 10/14/2010
• Est. Priority Date: 07/25/2005
• Status: Active Grant

• Current Assignee: Surf Communications Solutions
• Original Assignee: Surf Communications Solutions
• Inventors: Fisher, Abraham, Frydman, Daniel
• Granted Patent: US 7,991,940 B2
• Time in Patent Office: Days
• US Class Current: 710/315
• CPC Class Codes: H04L 69/08 Protocols for interworking; Protocol conversion
• CPC Class Codes: H04L 69/12 Protocol engines

Abstract

A signal processing board including a resource board substrate, an external interface on the board substrate, adapted to receive signals for processing, at least one slot adapted to receive a plug-in module with at least one processor thereon and an interface unit adapted to at least participate in converting signals exchanged between the external interface and a processor on a module received by the slot, between a format of signals received by the external interface and a signal format of the processor. The interface unit is suitable to at least participate in the conversion for a plurality of types of processors that differ in the format in which they transmit or receive signals.

Claims

1. A signal processing board, comprising:

a resource board substrate;

an external interface on the board substrate, adapted to receive signals for processing;

at least one slot adapted to receive a plug-in module with at least one processor thereon; and

an interface unit adapted to at least participate in converting signals exchanged between the external interface and a processor on a module received by the slot, between a format of signals received by the external interface and a signal format of the processor,

wherein the interface unit is suitable to at least participate in the conversion for a plurality of types of processors, differing in the format in which they transmit or receive signals.

3. A board according to claim 1, wherein the external interface comprises an AMC interface.

5. A board according to claim 1, wherein the interface unit is adapted to convert signals from the external interface into a format which is independent of the format of signals received by the external interface, except for characteristics of the format that effect the provision of the signals to the processor.

6. A board according to claim 1, wherein the interface unit is adapted to convert signals from the external interface into a format which is independent of a type of processor to which the signals are directed.

7. A board according to claim 1, wherein the interface unit is adapted to encapsulate signals from the external interface into packets in a format internal to the board and to send the encapsulated signals on toward the at least one slot.

8. A board according to claim 1, wherein the interface unit comprises a software or firmware configurable unit and wherein the board comprises a memory configured with a plurality of software or firmware processes from which a process is selected for the interface unit, according to a format of signals received by the external interface.

10. A board according to claim 1, comprising at least one module inserted into the at least one slot, the at least one module including one or more processors mounted thereon.

11. A board according to claim 10, comprising a translator mounted on the module, adapted to perform signal conversion tasks not performed by the interface unit, in converting between a format of signals received by the external interface and a format of the processor.

14. A board according to claim 11, comprising a memory storing at least one software or firmware process executable by the translator.

15. A board according to claim 14, wherein the memory storing the at least one process executable by the translator is mounted on the module including the translator.

57. A board according to claim 1, wherein the external interface is adapted to receive signals in accordance with a plurality of external formats and wherein the interface unit is configurable to participate in converting signals of a plurality of external formats.

58. A board according to claim 1, wherein the interface unit comprises a field programmable gate array FPGA.

2. (canceled)

4. (canceled)

9. (canceled)

12-13. -13. (canceled)

16. (canceled)

17. A plug-in module, comprising:

a module substrate including a connector adapted to fit in a slot of a processing board;

at least one processor mounted on the module substrate; and

at least one translator mounted on the module substrate, configured to convert signals directed to the at least one processor into a format supported by the processor.

19. A module according to claim 17, wherein the at least one translator is configurable with a software or firmware stored in a memory of a processing board on which the module is mounted.

18. (canceled)

20. A signal processing board, comprising:

a resource board substrate;

an external interface on the board substrate, adapted to receive signals for processing;

at least one processing module including at least one processor therein, mounted on the substrate; and

an interface unit adapted to at least participate in converting signals exchanged between the external interface and a processor of a module, between a format of signals received by the external interface and a signal format of the processor,

wherein the interface unit is suitable to at least participate in the conversion for a plurality of types of processors, differing in the format in which they transmit or receive signals.

21. A board according to claim 20, wherein the at least one processing module is detachably mounted on the substrate.

23. A board according to claim 20, wherein the interface unit is adapted to receive signals from the external interface and encapsulate the signals into packets in a format internal to the board.

25. A board according to claim 20, comprising one or more translators adapted to receive packets from the interface unit, to remove the encapsulation and to convert signals from the packets into a format of one of the processors.

22. (canceled)

24. (canceled)

26-27. -27. (canceled)

28. A multi-processor signal processing board, comprising:

a resource board substrate;

an external interface on the board substrate, adapted to receive signals for processing;

a plurality of processors mounted on the substrate arranged in a logical array of signal handling processors; and

an interface unit adapted to receive signals from the external interface and direct the signals to one or more of the processors for handling,

wherein at least two of the processors have different types of interfaces connecting to the interface unit.

29. A board according to claim 28, wherein the external interface comprises an AMC interface.

30. A board according to claim 28, comprising one or more translators adapted to convert signals directed to each of the processors into a format of the processor to which the signals are directed.

34. A board according to claim 30, wherein the one or more translators comprise field programmable gate arrays FPGAs.

41. A board according to claim 28, wherein the at least two processors of different types of external interfaces differ in the protocols in which they expect to receive signals.

44. A board according to claim 28, wherein the interface unit comprises a field programmable gate array FPGA.

31-33. -33. (canceled)

35-40. -40. (canceled)

42-43. -43. (canceled)

45-56. -56. (canceled)