DATA STORAGE DEVICE

• US 20100262757A1
• Filed: 08/07/2009
• Published: 10/14/2010
• Est. Priority Date: 04/08/2009
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Borchers, Albert T., Swing, Andrew T., Sprinkle, Robert S.
• Granted Patent: US 8,566,507 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A data storage device may include a first memory board having multiple memory chips and a controller board that is arranged and configured to operably connect to the first memory board. The controller board may include an interface to a host and a controller that is arranged and configured to control command processing for multiple different types of memory chips, automatically recognize a type of the memory chips on the first memory board, receive commands from the host using the interface, and execute the commands using the memory chips.

Claims

1. A data storage device comprising:

a first memory board comprising multiple memory chips; and

a controller board that is arranged and configured to operably connect to the first memory board, wherein the controller board comprises;

an interface to a host, and

a controller that is arranged and configured to;

control command processing for multiple different types of memory chips,

automatically recognize a type of the memory chips on the first memory board,

receive commands from the host using the interface, and

execute the commands using the memory chips.

2. The data storage device of claim 1 wherein the controller is a field programmable gate array (FPGA) controller.

3. The data storage device of claim 1 wherein the controller is arranged and configured to automatically recognize the type of the memory chips on the first memory board upon power up of the first memory board and the controller board.

4. The data storage device of claim 1 wherein the controller is arranged and configured to:

control command processing for multiple different types of memory chips,

automatically recognize the type of the memory chips on the first memory board,

receive commands from the host using the interface, and

execute the commands using the memory chips by translating the commands based on the type of the memory chips on the first memory board.

5. The data storage device of claim 1 wherein the controller is arranged and configured to control command processing for multiple different types of memory chips and to automatically recognize the type of the memory chips on the first memory board including memory chips manufactured by different vendors.

6. The data storage device of claim 1 wherein the controller is arranged and configured to control command processing for multiple different types of memory chips and to automatically recognize the type of the memory chips on the first memory board including single-level cell (SLC) NAND flash memory chips and multi-level cell (MLC) NAND flash memory chips.

7. The data storage device of claim 1 further comprising a second memory board comprising multiple memory chips wherein:

the controller board is arranged and configured to operably connect to the second memory board, and

the controller is arranged and configured to;

control command processing for multiple different types of memory chips,

automatically recognize the type of the memory chips on the second memory board,

receive commands from the host using the interface, and

execute the commands using the memory chips on both the first memory board and the second memory board.

8. The data storage device of claim 7 further comprising a third memory board comprising multiple memory chips and a fourth memory board comprising multiple memory chips wherein:

the controller board is arranged and configured to disconnect from the first memory board and the second memory board and to operably connect to the third memory board and the fourth memory board, and

the controller is arranged and configured to;

control command processing for multiple different types of memory chips,

automatically recognize the type of the memory chips on the third memory board and on the fourth memory board, wherein the type of the memory chips on the third memory board and the fourth memory board are a same type and the type of the memory chips on the third memory board and the fourth memory board are a different type from the memory chips on the first memory board and the second memory board,

receive commands from the host using the interface, and

execute the commands using the memory chips on both the third memory board and the fourth memory board.

9. The data storage device of claim 1 wherein the memory chips comprise dynamic random access memory (DRAM) chips.

10. The data storage device of claim 1 wherein the memory chips comprise phase change memory (PCM) chips.

11. The data storage device of claim 1 wherein the memory chips comprise flash memory chips.

12. The data storage device of claim 11 wherein:

the flash memory chips are NAND flash memory chips,

the interface is a PCI-e interface; and

the controller is a field programmable gate array (FPGA) controller.

13. A computing device comprising:

a host; and

a data storage device, the data storage device comprising;

a first memory board comprising multiple memory chips, and

a controller board that is arranged and configured to operably connect to the first memory board, wherein the controller board comprises;

an interface to the host, and

a controller that is arranged and configured to;

control command processing for multiple different types of memory chips,

automatically recognize a type of the memory chips on the first memory board,

receive commands from the host using the interface, and

execute the commands using the memory chips.

14. The computing device of claim 13 wherein the controller is a field programmable gate array (FPGA) controller.

15. The computing device of claim 13 wherein the controller is arranged and configured to:

control command processing for multiple different types of memory chips,

automatically recognize the type of the memory chips on the first memory board,

receive commands from the host using the interface, and

execute the commands using the memory chips by translating the commands based on the type of the memory chips on the first memory board.

16. The computing device of claim 13 wherein the controller is arranged and configured to control command processing for multiple different types of memory chips and to automatically recognize the type of the memory chips on the first memory board including memory chips manufactured by different vendors.

17. The computing device of claim 13 further comprising a second memory board comprising multiple memory chips wherein:

the controller board is arranged and configured to operably connect to the second memory board, and

the controller is arranged and configured to;

control command processing for multiple different types of memory chips,

automatically recognize the type of the memory chips on the second memory board,

receive commands from the host using the interface, and

execute the commands using the memory chips on both the first memory board and the second memory board.

18. The computing device of claim 13 wherein the memory chips comprise dynamic random access memory (DRAM) chips.

19. The computing device of claim 13 wherein the memory chips comprise phase change memory (PCM) chips.

20. The computing device of claim 13 wherein the memory chips comprise flash memory chips.

21. The computing device of claim 20 wherein:

the flash memory chips are NAND flash memory chips,

the interface is a PCI-e interface; and

the controller is a field programmable gate array (FPGA) controller.

22. A method, comprising:

receiving power at a controller board, wherein the controller board comprises an interface to a host and a controller, the controller being configured to control command processing for multiple different types of memory chips;

querying a first memory board for one or more characteristics of multiple memory chips secured to the first memory board;

automatically recognizing a type of the memory chips on the first memory board based on the one or more characteristics of the memory chips;

receiving commands from the host using the interface; and

executing the commands using the memory chips.

23. The method as in claim 22 wherein executing the commands using the memory chips comprises executing the commands using the memory chips by translating the commands based on the type of the memory chips on the first memory board.

24. The method as in claim 22 wherein automatically recognizing the type of the memory chips comprises automatically recognizing the type of the memory chips on the first memory board including memory chips manufactured by different vendors.

25. The method as in claim 22 wherein automatically recognizing the type of the memory chips comprises automatically recognizing the type of the memory chips on the first memory board including single-level cell (SLC) flash memory chips and multi-level cell (MLC) flash memory chips.

26. The method as in claim 22 further comprising:

connecting a second memory board to the controller board, the second memory board comprising multiple memory chips; and

automatically recognizing a type of the memory chips on the second memory board,

wherein executing the commands using the memory chips comprises executing the commands using the memory chips on both the first memory board and the second memory board.

27. The method as in claim 26 further comprising:

disconnecting the first memory board and the second memory board from the controller board;

connecting a third memory board and a fourth memory board to the controller board, the third memory board and the fourth memory board each comprising multiple memory chips; and

automatically recognizing a type of the memory chips on the third memory board and on the fourth memory board, wherein the type of the memory chips on the third memory board and the fourth memory board are a same type and the type of the memory chips on the third memory board and the fourth memory board are a different type from the memory chips on the first memory board and the second memory board,

wherein executing the commands using the memory chips comprises executing the commands using the memory chips on both the third memory board and the fourth memory board.

28. The method as in claim 22 wherein the memory chips comprise dynamic random access memory (DRAM) chips.

29. The method as in claim 22 wherein the memory chips comprise phase change memory (PCM) chips.

30. The method as in claim 22 wherein the memory chips comprise flash memory chips.

31. The method as in claim 30 wherein:

the flash memory chips are NAND flash memory chips,

the interface is a PCI-e interface; and

the controller is a field programmable gate array (FPGA) controller.