DATA STORAGE DEVICE

• US 20100262758A1
• Filed: 08/07/2009
• Published: 10/14/2010
• Est. Priority Date: 04/08/2009
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Borchers, Albert T., Swing, Andrew T., Sprinkle, Robert S.
• Granted Patent: US 8,205,037 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A data storage device may include a first memory board including multiple memory chips and a controller board that is arranged and configured to operably connect to the first memory board. The controller board may include an interface to a host and a controller that includes a power module and that is arranged and configured to control command processing for multiple memory chips having different voltages, automatically recognize a voltage of the memory chips on the first memory board, configure the power module to operate at the recognized voltage of the memory chips, receive commands from the host using the interface and execute the commands using the memory chips.

Claims

1. A data storage device comprising:

a first memory board comprising multiple memory chips; and

a controller board that is arranged and configured to operably connect to the first memory board, wherein the controller board comprises;

an interface to a host, and

a controller that comprises a power module and that is arranged and configured to;

control command processing for multiple memory chips having different voltages,

automatically recognize a voltage of the memory chips on the first memory board,

configure the power module to operate at the recognized voltage of the memory chips,

receive commands from the host using the interface, and

execute the commands using the memory chips.

2. The data storage device of claim 1 wherein the controller is a field programmable gate array (FPGA) controller.

3. The data storage device of claim 1 wherein the memory chips on the first memory board are configured to operate at a same voltage.

4. The data storage device of claim 1 wherein the controller is arranged and configured to automatically recognize the voltage of the memory chips on the first memory board upon power up of the first memory board and the controller board.

5. The data storage device of claim 1 wherein the controller is arranged and configured to:

control command processing for multiple memory chips having different voltages,

automatically recognize the voltage of the memory chips on the first memory board,

configure the power module to operate at the recognized voltage of the memory chips,

receive commands from the host using the interface, and

execute the commands using the memory chips without translating the commands based on the voltage of the memory chips on the first memory board.

6. The data storage device of claim 1 further comprising a second memory board comprising multiple memory chips wherein:

the controller board is arranged and configured to operably connect to the second memory board, and

the controller is arranged and configured to;

control command processing for multiple memory chips having different voltages,

automatically recognize a voltage of the memory chips on the second memory board,

configure the power module to operate at the recognized voltage of the memory chips on the first memory board and the second memory board,

receive commands from the host using the interface, and

execute the commands using the memory chips on both the first memory board and the second memory board.

7. The data storage device of claim 8 further comprising a third memory board comprising multiple memory chips and a fourth memory board comprising multiple memory chips wherein:

the controller board is arranged and configured to disconnect from the first memory board and the second memory board and to operably connect to the third memory board and the fourth memory board, and

the controller is arranged and configured to;

control command processing for multiple memory chips having different voltages,

automatically recognize a voltage of the memory chips on the third memory board and on the fourth memory board, wherein the voltage of the memory chips on the third memory board and the fourth memory board are a same voltage and the same voltage of the memory chips on the third memory board and the fourth memory board are a different voltage from the memory chips on the first memory board and the second memory board,

configure the power module to operate at the recognized voltage of the memory chips on the third memory board and the fourth memory board,

receive commands from the host using the interface, and

execute the commands using the memory chips on both the third memory board and the fourth memory board.

8. The data storage device of claim 1 wherein the memory chips comprise dynamic random access memory (DRAM) chips.

9. The data storage device of claim 1 wherein the memory chips comprise phase change memory (PCM) chips.

10. The data storage device of claim 1 wherein the memory chips comprise flash memory chips.

11. The data storage device of claim 10 wherein:

the flash memory chips are NAND flash memory chips,

the interface is a PCI-e interface; and

the controller is a field programmable gate array (FPGA) controller.

12. A computing device comprising:

a host; and

a data storage device, the data storage device comprising;

a first memory board comprising multiple memory chips; and

a controller board that is arranged and configured to operably connect to the first memory board, wherein the controller board comprises;

an interface to the host, and

a controller that comprises a power module and that is arranged and configured to;

control command processing for multiple memory chips having different voltages,

automatically recognize a voltage of the memory chips on the first memory board,

configure the power module to operate at the recognized voltage of the memory chips,

receive commands from the host using the interface, and

execute the commands using the memory chips.

13. The computing device of claim 12 wherein the controller is a field programmable gate array (FPGA) controller.

14. The computing device of claim 12 wherein the controller is arranged and configured to:

control command processing for multiple memory chips having different voltages,

automatically recognize the voltage of the memory chips on the first memory board,

configure the power module to operate at the recognized voltage of the memory chips,

receive commands from the host using the interface, and

execute the commands using the memory chips without translating the commands based on the voltage of the memory chips on the first memory board.

15. The computing device of claim 12 further comprising a second memory board comprising multiple memory chips wherein:

the controller board is arranged and configured to operably connect to the second memory board, and

the controller is arranged and configured to;

control command processing for multiple memory chips having different voltages,

automatically recognize a voltage of the memory chips on the second memory board,

configure the power module to operate at the recognized voltage of the memory chips on the first memory board and the second memory board,

receive commands from the host using the interface, and

execute the commands using the memory chips on both the first memory board and the second memory board.

16. The computing device of claim 12 wherein the memory chips comprise dynamic random access memory (DRAM) chips.

17. The computing device of claim 12 wherein the memory chips comprise phase change memory (PCM) chips.

18. The computing device of claim 12 wherein the memory chips comprise flash memory chips.

19. The computing device of claim 18 wherein:

the flash memory chips are NAND flash memory chips,

the interface is a PCI-e interface; and

the controller is a field programmable gate array (FPGA) controller.

20. A method, comprising:

receiving power at a controller board, wherein the controller board comprises an interface to a host and a controller, the controller comprising a power module and the controller being configured to control command processing for multiple memory chips having different voltages;

determining a voltage of multiple memory chips on a first memory board;

configuring the power module to operate at the determined voltage of the memory chips;

receiving commands from the host using the interface; and

executing the commands using the memory chips.

21. The method as in claim 20 wherein:

determining the voltage of the memory chips comprises sensing voltage pins on the first memory board; and

configuring the power module comprises configuring a DC-to-DC converter to the voltage sensed at the voltage pins on the first memory board.

22. The method as in claim 20 wherein executing the commands using the memory chips comprises executing the commands using the memory chips without translating the commands based on the voltage of the memory chips on the first memory board.

23. The method as in claim 20 further comprising:

connecting a second memory board to the controller board, the second memory board comprising multiple memory chips;

determining a voltage of the multiple memory chips on the second memory board; and

configuring the power module to operate at the determined voltage of the memory chips,

wherein executing the commands using the memory chips comprises executing the commands using the memory chips on both the first memory board and the second memory board.

24. The method as in claim 23 further comprising:

disconnecting the first memory board and the second memory board from the controller board;

connecting a third memory board and a fourth memory board to the controller, the third memory board and the fourth memory board each comprising multiple memory chips;

determining a voltage of the memory chips on the third memory board and the fourth memory board, wherein the voltage of the memory chips on the third memory board and the fourth memory board are a same voltage and the same voltage of the memory chips on the third memory board and the fourth memory board are a different voltage from the memory chips on the first memory board and the second memory board; and

configuring the power module to operate at the voltage of the third memory board and the fourth memory board,

wherein executing the commands using the memory chips comprises executing the commands using the memory chips on both the third memory board and the fourth memory board.

25. The method as in claim 20 wherein the memory chips comprise dynamic random access memory (DRAM) chips.

26. The method as in claim 20 wherein the memory chips comprise phase change memory (PCM) chips.

27. The method as in claim 20 wherein the memory chips comprise flash memory chips.

28. The method as in claim 27 wherein:

the flash memory chips are NAND flash memory chips,

the interface is a PCI-e interface; and

the controller is a field programmable gate array (FPGA) controller.