DATA STORAGE DEVICE

• US 20100262759A1
• Filed: 08/07/2009
• Published: 10/14/2010
• Est. Priority Date: 04/08/2009
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Klaus, Jason W., Borchers, Albert T., Swing, Andrew T., Sprinkle, Robert S.
• Granted Patent: US 8,578,084 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A data storage device may include a first memory board and a second memory board, where the first memory board and the second memory board each comprise multiple memory chips. The data storage device may include a controller board that is arranged and configured to operably connect to the first memory board and the second memory board, where the controller board includes a high speed interface and a controller that is arranged and configured to receive commands from a host using the high speed interface and to execute the commands, where the first memory board and the second memory board are each separately removable from the controller board.

Claims

1. A data storage device comprising:

a first memory board;

a second memory board, wherein;

the first memory board and the second memory board each comprise multiple memory chips; and

a controller board that is arranged and configured to operably connect to the first memory board and the second memory board, wherein the controller board comprises;

a high speed interface, and

a controller that is arranged and configured to receive commands from a host using the high speed interface and to execute the commands,

wherein the first memory board and the second memory board are each separately removable from the controller board.

2. The data storage device of claim 1 wherein the controller is a field programmable gate array (FPGA) controller.

3. The data storage device of claim 1 wherein the memory chips comprise flash memory chips.

4. The data storage device of claim 3 wherein the flash memory chips are single-level cell (SLC) NAND flash memory chips.

5. The data storage device of claim 3 wherein the flash memory chips are multi-level cell (MLC) NAND flash memory chips.

6. The data storage device of claim 1 wherein the high speed interface is a PCI-e interface.

7. The data storage device of claim 1 wherein the first memory board, the second memory board and the controller board are arranged and configured to fit in a drive bay of a server.

8. The data storage device of claim 1 wherein the first memory board is operably connected to a top side of the controller board and the second memory board is operably connected to a bottom side of the controller board.

9. The data storage device of claim 1 wherein the memory chips comprise dynamic random access memory (DRAM) chips.

10. The data storage device of claim 1 wherein the memory chips comprise phase change memory (PCM) chips.

11. The data storage device of claim 3 wherein:

the flash memory chips are NAND flash memory chips,

the high speed interface is a PCI-e interface; and

the controller is a field programmable gate array (FPGA) controller.

12. The data storage device of claim 1 wherein the first memory board and the second memory board are modular boards that are arranged and configured to be removed and replaced by another memory board comprising multiple memory chips.

13. The data storage device of claim 1 wherein the controller comprises a power module and is arranged and configured to:

control command processing for multiple memory chips having different voltages,

automatically recognize a voltage of the memory chips on the first memory board and the second memory board,

configure the power module to operate at the recognized voltage of the memory chips,

receive commands from the host using the interface, and

execute the commands using the memory chips.

14. The data storage device of claim 1 wherein the controller is arranged and configured to:

control command processing for multiple different types of memory chips,

automatically recognize a type of the memory chips on the first memory board and the second memory board,

receive commands from the host using the interface, and

execute the commands using the memory chips.

15. The data storage device of claim 1 wherein the controller comprises multiple channels, wherein each of the channels is associated with one or more of the memory chips and each of the memory chips is associated with one of the channels.

16. The data storage device of claim 15 wherein the controller further comprises a channel controller for each of the channels.

17. A computing device comprising:

a host; and

a data storage device, the data storage device comprising;

a first memory board;

a second memory board, wherein;

the first memory board and the second memory board each comprise multiple memory chips; and

a controller board that is arranged and configured to operably connect to the first memory board and the second memory board, wherein the controller board comprises;

a high speed interface, and

a controller that is arranged and configured to receive commands from the host using the high speed interface and to execute the commands,

wherein the first memory board and the second memory board are each separately removable from the controller board.

18. The computing device of claim 17 wherein the controller is a field programmable gate array (FPGA) controller.

19. The computing device of claim 17 wherein the memory chips comprise flash memory chips.

20. The computing device of claim 19 wherein the flash memory chips are single-level cell (SLC) NAND flash memory chips.

21. The computing device of claim 19 wherein the flash memory chips are multi-level cell (MLC) NAND flash memory chips.

22. The computing device of claim 17 wherein the high speed interface is a PCI-e interface.

23. The computing device of claim 17 wherein the first memory board, the second memory board and the controller board are arranged and configured to fit in a drive bay of a server.

24. The computing device of claim 19 wherein:

the flash memory chips are NAND flash memory chips,

the high speed interface is a PCI-e interface; and

the controller is a field programmable gate array (FPGA) controller.

25. The computing device of claim 17 wherein the first memory board and the second memory board are modular boards that are arranged and configured to be removed and replaced by another memory board comprising multiple memory chips.

26. The computing device of claim 17 wherein the memory chips comprise dynamic random access memory (DRAM) chips.

27. The computing device of claim 17 wherein the memory chips comprise phase change memory (PCM) chips.

28. A method for assembling a data storage device, the method comprising:

securing multiple memory chips to a first memory board;

securing multiple memory chips to a second memory board;

attaching a high speed interface and a controller to a controller board;

operably connecting the first memory board to the controller board; and

operably connecting the second memory board to the controller board, wherein the first memory board and the second memory board are each separately removable from the controller board.

29. The method as in claim 28 further comprising:

securing multiple memory chips to a third memory board;

disconnecting one of the first memory board or the second memory board from the controller board; and

operably connecting the third memory board to the controller board.

30. The method as in claim 28 wherein operably connecting the first memory board to the controller board and operably connecting the second memory board to the controller board comprise forming a drive bay form factor of the first memory board, the second memory board and the controller board such that the drive bay form factor is configured to fit in a drive bay of a server.

31. The method as in claim 28 wherein:

operably connecting the first memory board to the controller board comprises operably connecting the first memory board to a top side of the controller board; and

operably connecting the second memory board to the controller board comprises operably connecting the second memory board to a bottom side of the controller board.

32. The method as in claim 28 wherein the memory chips comprise dynamic random access memory (DRAM) chips.

33. The method as in claim 28 wherein the memory chips comprise phase change memory (PCM) chips.

34. The method as in claim 28 wherein the memory chips comprise flash memory chips.

35. The method as in claim 34 wherein:

the flash memory chips on the first memory board and the second memory are NAND flash memory chips,

the high speed interface is a PCI-e interface; and

the controller is a field programmable gate array (FPGA) controller.