COMMAND PROCESSOR FOR A DATA STORAGE DEVICE

• US 20100262760A1
• Filed: 08/07/2009
• Published: 10/14/2010
• Est. Priority Date: 04/08/2009
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Borchers, Albert T., Swing, Andrew T., Sprinkle, Robert S.
• Granted Patent: US 8,244,962 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

An apparatus for queuing and ordering commands for a data storage device may include a slot tracker module that is arranged and configured to track available slots for commands from a host, a command transfer module that is operably coupled to the slot tracker module and that is arranged and configured to retrieve commands from the host based on a number of the available slots, a pending command module that is operably coupled to the command transfer module and that is arranged and configured to queue and order the commands from the host for processing using an ordered list that is based on an age of the commands and a task dispatch module that is operably coupled to the pending command module and that is arranged and configured to dispatch the commands for processing using the ordered list from the pending command module and an availability of storage locations.

Claims

1. An apparatus for queuing and ordering commands for a data storage device, comprising:

a slot tracker module that is arranged and configured to track available slots for commands from a host;

a command transfer module that is operably coupled to the slot tracker module and that is arranged and configured to retrieve commands from the host based on a number of the available slots;

a pending command module that is operably coupled to the command transfer module and that is arranged and configured to queue and order the commands from the host for processing using an ordered list that is based on an age of the commands; and

a task dispatch module that is operably coupled to the pending command module and that is arranged and configured to dispatch the commands for processing using the ordered list from the pending command module and an availability of storage locations.

2. The apparatus of claim 1 wherein the task dispatch module is arranged and configured to use the ordered list from the pending command module to maintain an order of the commands as received from the host for the commands that are designated for a same storage location.

3. The apparatus of claim 1 wherein the task dispatch module is arranged and configured to dispatch the commands designated for different storage locations out of order.

4. The apparatus of claim 1 wherein:

the storage locations are arranged and configured into multiple channels with each of the channels including multiple flash memory chips; and

the task dispatch module is arranged and configured to maintain an order of the commands as received from the host for the commands that are designated for a same channel.

5. The apparatus of claim 1 wherein:

the storage locations are arranged and configured into multiple channels with each of the channels including multiple flash memory chips; and

the task dispatch module is arranged and configured to maintain an order of the commands as received from the host for the commands that are designated for a same flash memory chip.

6. The apparatus of claim 1 wherein:

the storage locations are arranged and configured into multiple channels with each of the channels including multiple flash memory chips; and

the task dispatch module is arranged and configured to dispatch the commands designated for different channels out of order.

7. The apparatus of claim 1 wherein:

the storage locations are arranged and configured into multiple channels with each of the channels including multiple flash memory chips; and

the task dispatch module is arranged and configured to dispatch the commands designated for different flash memory chips out of order.

8. The apparatus of claim 1 wherein the ordered list is a doubly linked list.

9. The apparatus of claim 8 wherein the doubly linked list is implemented in hardware.

10. The apparatus of claim 1 wherein the slot tracker module is arranged and configured to assign each of the commands a global slot identifier (ID) to track each of the commands and to track the number of the available slots.

11. The apparatus of claim 1 wherein the slot tracker module, the command transfer module, the pending command module and the task dispatch module are implemented in hardware as part of a field programmable gate array (FPGA) circuit.

12. A data storage device comprising:

multiple flash memory chips; and

a controller that is operably coupled to the flash memory chips and that is arranged and configured to receive commands from a host, wherein the controller comprises;

a command processor that is arranged and configured to;

queue and order the commands from the host using an ordered list that is based on an age of the commands,

dispatch the commands that are designated for a same flash memory chip in order using the ordered list, and

dispatch the commands that are designated for different flash memory chips out of order.

13. The data storage device of claim 12 wherein the controller is a field programmable gate array (FPGA) controller.

14. The data storage device of claim 12 wherein:

the flash memory chips are arranged and configured into multiple channels with each of the channels including one or more of the flash memory chips; and

the command processor is arranged and configured to;

dispatch the commands that are designated for a same channel in order using the ordered list, and

dispatch the commands that are designated for different channels out of order.

15. The data storage device of claim 12 wherein the command processor is arranged and configured to:

track available slots for commands from a host; and

retrieve commands from the host based on a number of the available slots.

16. The data storage device of claim 12 wherein the ordered list is a doubly linked list.

17. The data storage device of claim 12 wherein the command processor comprises:

a slot tracker module that is arranged and configured to track available slots for commands from a host;

a command transfer module that is operably coupled to the slot tracker module and that is arranged and configured to retrieve commands from the host based on a number of the available slots;

a pending command module that is operably coupled to the command transfer module and that is arranged and configured to queue and order the commands from the host for processing using an ordered list that is based on an age of the commands; and

a task dispatch module that is operably coupled to the pending command module and that is arranged and configured to dispatch the commands for processing using the ordered list from the pending command module and an availability of the flash memory chips.

18. The data storage device of claim 12 further comprising:

a memory board on which the flash memory chips are arranged and configured into multiple channels, with each of the channels being associated with one or more of the flash memory chips; and

a controller board that is operably connected to the memory board, wherein the controller board comprises;

a high speed interface; and

the controller that is arranged and configured to receive the commands from the host using the high speed interface.

19. The data storage device of claim 18 wherein:

the high speed interface is a PCI-e interface; and

the controller is a field programmable gate array (FPGA) controller.

20. The data storage device of claim 12 further comprising:

two memory boards on which the flash memory chips are arranged and configured into multiple channels, with each of the channels being associated with one or more of the flash memory chips; and

a controller board that is operably connected to the memory boards, wherein the controller board comprises;

a high speed interface; and

the controller that is arranged and configured to receive the commands from the host using the high speed interface, wherein the memory boards are each separately removable from the controller board.

21. A method for queuing and ordering commands for a data storage device, the method comprising:

tracking available slots for commands from a host;

retrieving commands from the host based on a number of the available slots;

queuing and ordering the commands from the host for processing using an ordered list that is based on an age of the commands; and

dispatching the commands for processing using the ordered list and an availability of storage locations.

22. The method as in claim 21 further comprising maintaining an order of the commands as received from the host for the commands that are designated for a same storage location.

23. The method as in claim 21 further comprising dispatching commands designated for different storage locations out of order.

24. The method as in claim 21 further comprising assigning each of the commands a global slot identifier (ID) to track each of the commands and to track the number of the available slots.