PARTITIONING A FLASH MEMORY DATA STORAGE DEVICE

• US 20100262761A1
• Filed: 08/07/2009
• Published: 10/14/2010
• Est. Priority Date: 04/08/2009
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Borchers, Albert T., Swing, Andrew T., Sprinkle, Robert S.
• Granted Patent: US 8,639,871 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A method of partitioning a data storage device that has a plurality of memory chips includes determining a number memory chips in the data storage device, defining, via a host coupled to the data storage device, a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips, defining a second partition of the data storage device via the host where the second partition includes a second subset of the plurality of memory chips, such that the first subset does not include any memory chips of the second subset and wherein the second subset does not include any memory chips of the first subset.

Claims

1. A method of partitioning a data storage device, wherein the device includes a plurality of memory chips, the method comprising:

determining a number memory chips in the data storage device;

defining, via a host coupled to the data storage device, a first partition of the data storage device, wherein the first partition includes a first subset of the plurality of memory chips;

defining a second partition of the data storage device via a host coupled to the data storage device, wherein the second partition includes a second subset of the plurality of memory chips;

wherein the first subset does not include any memory chips of the second subset and wherein the second subset does not include any memory chips of the first subset.

2. The method of claim 1, further comprising:

writing data to the first partition while reading data from the second partition.

3. The method of claim 1, wherein determining a number memory chips in the data storage device includes transmitting information from the data storage device to the host indicating the number of memory chips in the data storage device.

4. The method of claim 1, further comprising defining, in the host, an address location in the data storage device to which to write data from the host, wherein the address location specifies that the data be written to a specific one of the plurality of memory chips.

5. The method of claim 1, wherein the data storage device includes a plurality of physical channels for communication of data between the host and the plurality of memory chips, each channel being operably connected to a different plurality of the memory chips, the method further comprising:

determining the number of physical channels;

determining a first subset of the channels, wherein channels of the first subset of the channels are operably connected only to memory chips of the first subset of memory chips;

determining a second subset of the channels, wherein channels of the second subset of the channels are operably connected only to memory chips of the second subset of memory chips; and

defining, in the host, an address location in the data storage device to which to write data from the host, wherein the address location specifies that the data be written to a specific one of the plurality of memory chips through a specific channel.

6. The method of claim 3, wherein the first partition includes memory chips that are operably connected to a single channel.

7. The method of claim 1, further comprising:

re-defining, via the host coupled to the data storage device, the first partition of the data storage device to include a third subset of the plurality of memory chips,

wherein the third subset is different from the first subset, and

wherein the third subset does not include any memory chips of the second subset and wherein the second subset does not include any memory chips of the third subset.

8. The method of claim 1, further comprising:

receiving an indication that one of the memory chips in the first subset has failed or is approaching failure;

wherein re-defining the first partition includes defining the third subset as the first subset of memory chips but for the memory chip that has failed or that is approaching failure.

9. An apparatus comprising:

a data storage device including a plurality of memory chips;

a host operably coupled to the data storage device via an interface, the host comprising;

a configuration detection engine configured to detect the number of memory chips in the data storage device;

a partition engine configured to define a first partition of the data storage device, wherein the first partition includes a first subset of the plurality of memory chips and to define a second partition of the data storage device, wherein the second partition includes a second subset of the plurality of memory chips;

wherein the first subset does not include any memory chips of the second subset and wherein the second subset does not include any memory chips of the first subset.

10. The apparatus of claim 9, wherein the data storage device is configured to transmit, upon receiving a command from the host, information from the data storage device to the host indicating the number of memory chips in the data storage device.

11. The apparatus of claim 9, wherein the host further comprises an address assignment engine configured to assign a memory address to data to be written to the data storage device, wherein the assigned memory address specifies that the data be written to a specific one of the plurality of memory chips.

12. The apparatus of claim 9, wherein the data storage device includes a plurality of physical channels for communication of data between the host and the plurality of memory chips, each channel being operably connected to a different plurality of the memory chips, and

wherein the configuration detection engine is further configured to detect the number of channels in the data storage device;

wherein the partition engine is further configured to define a first subset of the channels, wherein channels of the first subset of the channels are operably connected only to memory chips of the first subset of memory chips; and

wherein the partition engine is further configured to define a second subset of the channels, wherein channels of the second subset of the channels are operably connected only to memory chips of the second subset of memory chips.

13. The apparatus of claim 12, wherein the host further comprises an address assignment engine configured to assign a memory address to data to be written to the data storage device, wherein the assigned memory address specifies that the data be written to a specific one of the plurality of memory chips through a specific channel.

14. The apparatus of claim 12, wherein the first partition includes memory chips that are operably connected to a single channel.

15. The apparatus of claim 9, wherein the partition engine is further configured to re-define the first partition of the data storage device to include a third subset of the plurality of memory chips,

wherein the third subset is different from the first subset, and

wherein the third subset does not include any memory chips of the second subset and wherein the second subset does not include any memory chips of the third subset.

16. The apparatus of claim 15, wherein the partition engine is further configured to receive an indication that one of the memory chips in the first subset has failed or is approaching failure;

and

wherein re-defining the first partition to include the third subset of the plurality of memory chips includes defining the third subset as the first subset of memory chips but for the memory chip that has failed or that is approaching failure.

17. A method of partitioning a data storage device, wherein the device includes a plurality of memory chips, the method comprising:

reading a physical configuration of the data storage device, including the number memory chips in the data storage device;

reading a partitioning scheme for the data storage device;

defining, via a host coupled to the data storage device, a first partition of the data storage device, wherein the first partition includes a first subset of the plurality of memory chips;

allocating a logical to physical memory map for the first partition;

defining, via a host coupled to the data storage device, a second partition of the data storage device, wherein the second partition includes a second subset of the plurality of memory chips; and

allocating a logical to physical memory map for the first partition,

wherein the first subset does not include any memory chips of the second subset and wherein the second subset does not include any memory chips of the first subset.

18. The method of claim 17, further comprising:

writing data to the first partition while reading data from the second partition.

19. The method of claim 17, wherein the data storage device includes a plurality of physical channels for communication of data between the host and the plurality of memory chips, each channel being operably connected to a different plurality of the memory chips, wherein the physical configuration of the data storage device further includes the number memory chips in the data storage device, the method further comprising:

determining a first subset of the channels, wherein channels of the first subset of the channels are operably connected only to memory chips of the first subset of memory chips;

determining a second subset of the channels, wherein channels of the second subset of the channels are operably connected only to memory chips of the second subset of memory chips; and

defining, in the host, an address location in the data storage device to which to write data from the host, wherein the address location specifies that the data be written to a specific one of the plurality of memory chips through a specific channel.

20. An apparatus comprising:

a data storage device including a plurality of memory chips;

a host operably coupled to the data storage device via an interface, the host comprising;

a configuration detection engine configured to read a physical configuration of the data storage device, including the number memory chips in the data storage device and configured to read a partitioning scheme for the data storage device;

a partition engine configured to define a first partition of the data storage device, wherein the first partition includes a first subset of the plurality of memory chips and to define a second partition of the data storage device, wherein the second partition includes a second subset of the plurality of memory chips, and configured to allocate a logical to physical memory map for the first partition and to allocate a logical to physical memory map for the second partition;

wherein the first subset does not include any memory chips of the second subset and wherein the second subset does not include any memory chips of the first subset.

21. The apparatus of claim 20, wherein the data storage device is configured to transmit, upon receiving a command from the host, information from the data storage device to the host indicating the physical configuration of the data storage device.

22. The apparatus of claim 20, wherein the data storage device includes a plurality of physical channels for communication of data between the host and the plurality of memory chips, each channel being operably connected to a different plurality of the memory chips, and

wherein the physical configuration of the data storage device further includes the number channels in the data storage device;

wherein the partition engine is further configured to define a first subset of the channels, wherein channels of the first subset of the channels are operably connected only to memory chips of the first subset of memory chips; and

wherein the partition engine is further configured to define a second subset of the channels, wherein channels of the second subset of the channels are operably connected only to memory chips of the second subset of memory chips.

23. The apparatus of claim 22, wherein the first partition includes memory chips that are operably connected to a single channel.