DATA STORAGE DEVICE

• US 20100262767A1
• Filed: 04/07/2010
• Published: 10/14/2010
• Est. Priority Date: 04/08/2009
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Klaus, Jason W., Borchers, Albert T., Swing, Andrew T., Sprinkle, Robert S.
• Granted Patent: US 8,433,845 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/88 with partially good memories

Abstract

A data storage device may include a command bus, a status bus, multiple memory devices that are operably coupled to the command bus and to the status bus, and a controller including multiple channel controllers, where the channel controllers are operably coupled to the command bus and to the status bus and each of the channel controllers is arranged and configured to control one or more of the memory devices. The data storage device may include multiple programmable logic devices that are operably coupled to the status bus, where each of the programmable logic devices is configured to retrieve a ready/busy signal from each of the memory devices under control of one of the channel controllers using the status bus, serialize the ready/busy signals and communicate the serialized ready/busy signals to the channel controllers.

Claims

1. A data storage device comprising:

a command bus;

a status bus;

multiple memory devices that are operably coupled to the command bus and to the status bus;

a controller comprising multiple channel controllers, wherein the channel controllers are operably coupled to the command bus and to the status bus and each of the channel controllers is arranged and configured to control one or more of the memory devices; and

multiple programmable logic devices that are operably coupled to the status bus, wherein each of the programmable logic devices is configured to;

retrieve a ready/busy signal from each of the memory devices under control of one of the channel controllers using the status bus;

serialize the ready/busy signals; and

communicate the serialized ready/busy signals to the channel controllers.

2. The data storage device of claim 1 wherein the memory devices comprise flash memory chips.

3. The data storage device of claim 1 wherein the memory devices comprise dynamic random access memory (DRAM) chips.

4. The data storage device of claim 1 wherein the each of the channel controllers is configured to de-serialize the read/busy signals received from the programmable logic devices controlled by the channel controller.

5. The data storage device of claim 1 wherein each of the channel controllers receives a status of the controlled memory devices without polling the status of the controlled memory devices over the command bus.

6. The data storage device of claim 1 the status bus comprises an out-of-band bus that is configured to facilitate communication of a status of the memory devices to the channel controllers.

7. The data storage device of claim 1 further comprising:

a memory board, wherein the memory devices are affixed to the memory board; and

a controller board that is separate from the memory board and that is operably connected to the memory board, wherein the controller is affixed to the controller board.

8. The data storage device of claim 7 wherein the programmable logic devices are affixed to the memory board.

9. A method for determining a status of multiple memory devices, the method comprising:

retrieving, by a programmable logic device, a ready/busy signal from each of multiple memory devices;

serializing the retrieved ready/busy signals; and

communicating the serialized ready/busy signals from the programmable logic device to a channel controller.

10. The method as in claim 9 wherein the multiple memory devices comprise flash memory chips.

11. The method as in claim 9 wherein the multiple memory devices comprise dynamic random access memory (DRAM) chips.

12. The method as in claim 9 wherein retrieving the ready/busy signal comprises retrieving the ready/busy signal from each of the memory devices using an out-of-band status bus.

13. The method as in claim 9 wherein:

retrieving, by the programmable logic device, comprises retrieving, by the programmable logic device, a ready/busy signal from each of a first group of memory devices controlled by a first channel controller and retrieving, by the programmable logic device, a ready/busy signal from each of a second group of memory devices controlled by a second channel controller;

serializing the retrieved ready/busy signals comprises serializing the retrieved ready/busy signals from the first group of memory devices and the second group of memory devices; and

communicating the serialized ready/busy signals comprises communicating the serialized ready/busy signals from the programmable logic device to the first channel controller and the second channel controller.

14. A programmable logic device comprising instructions that are tangibly embodied on the programmable logic device, wherein the instructions that, when executed, cause the programmable logic device to:

retrieve a ready/busy signal from each of multiple memory devices;

serialize the retrieved ready/busy signals; and

communicate the serialized ready/busy signals to a channel controller.

15. The programmable logic device of claim 14 wherein the memory devices comprise flash memory chips.

16. The programmable logic device of claim 14 wherein the memory devices comprise dynamic random access memory (DRAM) chips.

17. The programmable logic device of claim 14 wherein the instructions that, when executed, cause the programmable logic device to retrieve the ready/busy signal comprise instructions that, when executed, cause the programmable logic device to retrieve the ready/busy signal from each of the memory devices using an out-of-band status bus.

18. The programmable logic device of claim 14 wherein the programmable logic device is on a memory board and the channel controller is on a separate controller board.

19. The programmable logic device of claim 14 wherein the instructions that, when executed, cause the programmable logic device to communicate the serialized ready/busy signals comprise instructions that, when executed, cause the programmable logic device to communicate the serialized ready/busy signals to the channel controller without being polled by the channel controller.