DATA STRIPING IN A FLASH MEMORY DATA STORAGE DEVICE

• US 20100262773A1
• Filed: 08/07/2009
• Published: 10/14/2010
• Est. Priority Date: 04/08/2009
• Status: Abandoned Application

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Borchers, Albert T., Swing, Andrew T., Sprinkle, Robert S.
• Application Number:
  US12/537,738
• Publication Number:
  US 20100262773A1
• Time in Patent Office: Days
• US Class Current: 711/114
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A method is disclosed for striping data from a host to a data storage device that includes a plurality of memory chips and a plurality of physical channels for communication of data between the host and the plurality of memory chips, where each channel is operably connected to a different plurality of the memory chips. The method includes determining a number of physical channels in the plurality of channels, determining a first channel chunk size with which to write data to memory chips connected to separate channels, segmenting, via the host, logically sequential data into first channel chunk size segments, and striping data to different channels of the data storage device in first channel chunk size units.

Claims

1. A method of striping data from a host to a data storage device that includes a plurality of memory chips and a plurality of physical channels for communication of data between the host and the plurality of memory chips, each channel being operably connected to a different plurality of the memory chips, the method comprising:

determining a number of physical channels in the plurality of channels;

for each of the determined physical channels, determining a number of memory chips operably connected to the channel;

determining a first channel chunk size with which to write data to memory chips connected to separate channels;

determining a chip chunk size with which to write data to different memory chips;

segmenting, via the host, logically sequential data into first channel chunk size segments;

segmenting, via the host, the first channel chunk size segments into chip chunk size segments;

striping data to different channels of the data storage device in first channel chunk size units; and

striping data in a first channel chuck sized segment to different memory chips connected to a channel in chip chunk size units.

2. The method of claim 1, wherein the logically sequential data consists of a data file.

3. The method of claim 1, further comprising:

writing data to a first channel while reading data from a second channel.

4. The method of claim 1, wherein determining the number of physical channels in the plurality of channels includes transmitting information from the data storage device to the host indicating the number of channels in the data storage device.

5. The method of claim 1, wherein determining the number of physical channels in the plurality of channels includes reading data stored on the host indicating the number of channels in the data storage device.

6. The method of claim 1, further comprising:

determining a second channel chunk size with which to write data to memory chips connected to separate channels;

segmenting, via the host, logically sequential data into second channel chunk size segments;

striping data to different channels of the data storage device in second channel chunk size units; and

striping data in a second channel chuck sized segment to different memory chips connected to a channel in chip chunk size units.

7. The method of claim 1, wherein the determining of the first channel chunk sized is based on input from a user entered via the host.

8. A method of striping data from a host to a data storage device that includes a plurality of memory chips and a plurality of physical channels for communication of data between the host and the plurality of memory chips, each channel being operably connected to a different plurality of the memory chips, the method comprising:

determining a number of physical channels in the plurality of channels;

determining a first channel chunk size with which to write data to memory chips connected to separate channels;

segmenting, via the host, logically sequential data into first channel chunk size segments; and

striping data to different channels of the data storage device in first channel chunk size units.

9. The method of claim 8, wherein the logically sequential data consists of a data file.

10. The method of claim 8, further comprising:

writing data to a first channel while reading data from a second channel.

11. The method of claim 8, wherein determining the number of physical channels in the plurality of channels includes transmitting information from the data storage device to the host indicating the number of channels in the data storage device.

12. The method of claim 8, wherein determining the number of physical channels in the plurality of channels includes reading data stored on the host indicating the number of channels in the data storage device.

13. The method of claim 8, further comprising:

determining a second channel chunk size with which to write data to memory chips connected to separate channels;

segmenting, via the host, logically sequential data into second channel chunk size segments; and

striping data to different channels of the data storage device in second channel chunk size units.

14. The method of claim 8, wherein the determining of the first channel chunk sized is based on input from a user entered via the host.

15. An apparatus comprising:

a data storage device including a plurality of memory chips and a plurality of physical channels for communication of data between a host and the plurality of memory chips, each channel being operably connected to a different plurality of the memory chips;

a host operably coupled to the data storage device via an interface, the host comprising;

an initialization engine configured to determine a first channel chunk size with which to write data to memory chips connected to separate channels;

a segmentation engine configured to segment logically sequential data into first channel chunk size segments; and

a striping engine configured to stripe data to different channels of the data storage device in first channel chunk size units.

16. The apparatus of claim 15, wherein the data storage device comprises a storage medium configured to store the number of channels and wherein the data storage device is configured to transmit, upon receiving a command from the host, information from the data storage device to the host indicating the number of channels in the data storage device.

17. The apparatus of claim 15, wherein the host further comprises an address assignment engine configured to assign a memory address to data to be written to the data storage device, wherein the assigned memory address specifies that the data be written to a specific one of the channels.

18. The apparatus of claim 15, wherein the logically sequential data consists of a data file.

19. The apparatus of claim 15, wherein the striping engine is configured to write data to a first channel while reading data from a second channel.

20. The apparatus of claim 15,

wherein the initialization engine is further configured to determine a second channel chunk size, different from the first channel chunk size, with which to write data to memory chips connected to separate channels;

wherein the segmentation engine is further configured to segment logically sequential data into second channel chunk size segments; and

wherein the striping engine is further configured to stripe data to different channels of the data storage device in second channel chunk size units.

21. The apparatus of claim 15, further comprising:

wherein the initialization engine is further configured to determine a chip chunk size with which to write data to different memory chips;

wherein the segmentation engine is further configured to segment the first channel chunk size segments into chip chunk size segments; and

wherein the striping engine is further configured to stripe data to different chips connected to a channel in first channel chunk size units.