Mode-Based Castout Destination Selection

• US 20100262783A1
• Filed: 04/09/2009
• Published: 10/14/2010
• Est. Priority Date: 04/09/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Starke, William J., Stuecheli, Jeffrey A., Guthrie, Guy L., Williams, Phillip G., Helterhoff, Harmony L.
• Granted Patent: US 8,312,220 B2
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/12 Replacement control

Abstract

In response to a data request of a first of a plurality of processing units, the first processing unit selects a victim cache line to be castout from the lower level cache of the first processing unit and determines whether a mode is set. If not, the first processing unit issues on the interconnect fabric an LCO command identifying the victim cache line and indicating that a lower level cache is the intended destination. If the mode is set, the first processing unit issues a castout command with an alternative intended destination. In response to a coherence response to the LCO command indicating success of the LCO command, the first processing unit removes the victim cache line from its lower level cache, and the victim cache line is held elsewhere in the data processing system. The mode can be set to inhibit castouts to system memory, for example, for testing.

Claims

1. A method of data processing in a data processing system including a system memory and an interconnect fabric coupled to plurality of processing units each including a respective processor core and associated upper and lower level caches, said method comprising:

in response to a data request of the processor core of a first processing unit among the plurality of processing units, selecting a victim cache line to be castout from the lower level cache of the first processing unit;

determining whether a mode is set for the first processing unit;

in response to a determination that the mode is set, the first processing unit issuing a lateral castout (LCO) command on the interconnect fabric, wherein the LCO command identifies the victim cache line to be castout from the lower level cache of the first processing unit and indicates that a lower level cache is the intended destination of the victim cache line;

in response to a determination that the mode is not set in the first processing unit, the first processing unit issuing on the interconnect fabric a castout command with an alternative intended destination; and

in response to a coherence response to the LCO command indicating success of the LCO command, removing the victim cache line from the lower level cache of the first processing unit and holding the victim cache line elsewhere in the data processing system.

2. The method of claim 1, wherein the lower level caches are victim caches, and wherein the first processing unit performs the selecting and removing steps.

3. The method of claim 1, and further comprising:

selecting the lower level cache of a second processing unit among the plurality of processing units as the intended destination of the LCO command and specifying the lower level cache of the second processing unit as the intended destination in the LCO command.

4. The method of claim 3, wherein the selecting includes:

determining the lower level cache of the second processing unit and another candidate lower level cache; and

selecting the lower level cache of the second processing unit as the intended destination if the mode is set and otherwise selecting said another candidate lower level cache as the alternative intended destination.

5. The method of claim 1, wherein selecting the victim cache line includes:

determining membership of each of a plurality of cache lines within a congruence class in either a first class of cache lines more likely to be accessed by the processor core of the first processing unit or a second class less likely to be accessed by the processor core of the first processing unit; and

selecting as the victim cache line one of one or more cache lines in the second class.

6. The method of claim 1, wherein holding the victim cache line elsewhere in the data processing system comprises:

in response to receipt of the LCO command, the lower level cache of a third processing unit among the plurality of processing units accepting the LCO command and holding the victim cache line.

7. The method of claim 1, wherein:

the alternative intended destination is system memory; and

the method further comprises in inhibiting all castout commands indicating system memory as an intended destination if the mode is set.

8. A data processing system, comprising:

an interconnect fabric; and

a plurality of processing units coupled to the interconnect fabric, the plurality of processing units each including a respective processor core and associated upper and lower level caches, wherein the plurality of processing units includes at least first, second and third processing units;

wherein the first processing unit, responsive to a data request, selects a victim cache line to be castout from its lower level cache and determines whether a mode is set for the first processing unit;

wherein the first processing unit, responsive to determining that the mode is set, issues a lateral castout (LCO) command on the interconnect fabric, the LCO command identifying the victim cache line to be castout from the lower level cache of the first processing unit and indicating that a lower level cache is the intended destination of the victim cache line;

wherein, responsive to a determination that the mode is not set in the first processing unit, the first processing unit issues on the interconnect fabric a castout command with an alternative intended destination; and

wherein responsive to a coherence response to the LCO command indicating success of the LCO command, the first processing unit removes the victim cache line from its lower level cache and the victim cache line is held elsewhere in the data processing system.

9. The data processing system of claim 8, wherein the lower level caches are victim caches.

10. The data processing system of claim 8, wherein the first processing unit selects the lower level cache of the second processing unit as the intended destination of the LCO command and specifies the lower level cache of the second processing unit as the intended destination in the LCO command.

11. The data processing system of claim 10, wherein the first processing unit determines the lower level cache of the second processing unit and another candidate lower level cache and selects the lower level cache of the second processing unit as the intended destination if the mode is set and otherwise selects said another candidate lower level cache as the alternative intended destination.

12. The data processing system of claim 8, wherein selecting the victim cache line includes:

determining membership of each of a plurality of cache lines within a congruence class in either a first class of cache lines more likely to be accessed by the processor core of the first processing unit or a second class less likely to be accessed by the processor core of the first processing unit; and

selecting as the victim cache line one of one or more cache lines in the second class.

13. The data processing system of claim 8, wherein, responsive to receipt of the LCO command, the lower level cache of the third processing unit accepts the LCO command and holds the victim cache line.

14. The data processing system of claim 8, wherein:

the alternative intended destination is system memory; and

the first processing unit inhibits all castout commands of the first processing unit that indicate system memory as an intended destination if the mode is set.

15. A processing unit for a data processing system including a plurality of processing units coupled by an interconnect fabric, the plurality of processing units including the processing unit as a first processing unit and additional second and third processing units, said first processing unit comprising:

a processor core and associated upper and lower level caches;

wherein the first processing unit, responsive to a data request, selects a victim cache line to be castout from its lower level cache and determines whether a mode is set for the first processing unit;

wherein the first processing unit, responsive to determining that the mode is set, issues a lateral castout (LCO) command on the interconnect fabric, the LCO command identifying the victim cache line to be castout from the lower level cache of the first processing unit and indicating that a lower level cache is the intended destination of the victim cache line;

wherein, responsive to a determination that the mode is not set in the first processing unit, the first processing unit issues on the interconnect fabric a castout command with an alternative intended destination; and

wherein responsive to a coherence response to the LCO command indicating success of the LCO command, the first processing unit removes the victim cache line from its lower level cache and the victim cache line is held elsewhere in the data processing system.

16. The processing unit of claim 15, wherein:

the lower level cache is a victim cache; and

the processing unit is a single integrated circuit chip.

17. The processing unit of claim 15, wherein the first processing unit selects the lower level cache of the second processing unit as the intended destination of the LCO command and specifies the lower level cache of the second processing unit as the intended destination in the LCO command.

18. The processing unit of claim 17, wherein the first processing unit determines the lower level cache of the second processing unit and another candidate lower level cache and selects the lower level cache of the second processing unit as the intended destination if the mode is set and otherwise selects said another candidate lower level cache as the alternative intended destination.

19. The processing unit of claim 15, wherein, responsive to receipt of the LCO command, the lower level cache of the third processing unit accepts the LCO command and holds the victim cache line.

20. The processing unit of claim 15, wherein:

the alternative intended destination is system memory; and

the first processing unit inhibits all castout commands of the first processing unit that indicate system memory as an intended destination if the mode is set.