Empirically Based Dynamic Control of Acceptance of Victim Cache Lateral Castouts

• US 20100262784A1
• Filed: 04/09/2009
• Published: 10/14/2010
• Est. Priority Date: 04/09/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Starke, William J., Stuecheli, Jeffrey A., Guthrie, Guy L., Helterhoff, Harmony L., Williams, Philip G., Ng, Alvan W., Jeremiah, Thomas L.
• Granted Patent: US 8,327,073 B2
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning

Abstract

A second lower level cache receives an LCO command issued by a first lower level cache on an interconnect fabric. The LCO command indicates an address of a victim cache line to be castout from the first lower level cache and indicates that the second lower level cache is an intended destination of the victim cache line. The second lower level cache determines whether to accept the victim cache line from the first lower level cache based at least in part on the address of the victim cache line indicated by the LCO command. In response to determining not to accept the victim cache line, the second lower level cache provides a coherence response to the LCO command refusing the identified victim cache line. In response to determining to accept the victim cache line, the second lower level cache updates an entry corresponding to the identified victim cache line.

Claims

1. A method of data processing in a data processing system including a plurality of processing units including a first processing unit and a second processing unit coupled by an interconnect fabric, wherein the first processing unit has a first processor core and associated first upper and first lower level caches and the second processing unit has a second processor core and associated second upper and lower level caches, said method comprising:

receiving on the interconnect fabric at the second lower level cache an LCO command issued by the first lower level cache, wherein the LCO command indicates an address of a victim cache line to be castout from the first lower level cache and indicates that the second lower level cache is an intended destination of the victim cache line;

the second lower level cache determining whether to accept the victim cache line from the first lower level cache based at least in part on the address of the victim cache line indicated by the LCO command;

in response to determining not to accept the victim cache line, providing a coherence response to the LCO command refusing the identified victim cache line; and

in response to determining to accept the victim cache line, updating an entry of the second lower level cache corresponding to the identified victim cache line.

2. The method of claim 1, wherein the first and second lower level caches are victim caches.

3. The method of claim 1, wherein the determining includes the second lower level cache determining if the address of the victim cache line falls within a guest LCO address region, and if so, accepting the identified victim cache line.

4. The method of claim 3, wherein the determining comprises:

if the address of the victim cache line falls outside the guest LCO address region, the second lower level cache determining by reference to an empirical metric of performance of the second upper level cache whether to accept the victim cache line.

5. The method of claim 4, wherein:

the method further comprises empirically measuring an effect of accepting victim cache lines that are specified by LCO commands and that have addresses within the guest LCO address region to obtain the empirical metric.

6. The method of claim 5, wherein empirically measuring an effect comprises empirically measuring an effect on cache capacity for castouts from the second upper level cache.

7. The method of claim 6, wherein:

the second lower level cache has a home LCO address region;

wherein empirically measuring an effect includes comparing hit rates of the second upper level cache in the home and guest LCO address regions.

8. The method of claim 1, wherein said determining comprises determining whether acceptance of the victim cache line will adversely impact cache bandwidth.

9. The method of claim 1, and further comprises reducing a probability that the second lower level cache will accept the victim cache line by reducing a number of storage locations in the second lower level cache allocable to receive victim cache line via LCO commands.

10. A data processing system, comprising:

a plurality of processing units including a first processing unit and a second processing unit coupled by an interconnect fabric, wherein the first processing unit has a first processor core and associated first upper and first lower level caches and the second processing unit has a second processor core and associated second upper and lower level caches;

wherein the second lower level cache, responsive to receiving on the interconnect fabric an LCO command issued by the first lower level cache, the LCO command indicating an address of a victim cache line to be castout from the first lower level cache and indicating that the second lower level cache is an intended destination of the victim cache line, determines whether to accept the victim cache line from the first lower level cache based at least in part on the address of the victim cache line indicated by the LCO command;

wherein the second lower level cache, responsive to determining not to accept the victim cache line, provides a coherence response to the LCO command refusing the identified victim cache line, and responsive to determining to accept the victim cache line, updates an entry of the second lower level cache corresponding to the identified victim cache line.

11. The data processing system of claim 10, wherein the first and second lower level caches are victim caches.

12. The data processing system of claim 10, wherein the second lower level cache determines if the address of the victim cache line falls within a guest LCO address region, and if so, accepts the identified victim cache line.

13. The data processing system of claim 12, wherein the second lower level cache, if the address of the victim cache line falls outside the guest LCO address region, determines by reference to an empirical metric of performance of the second upper level cache whether to accept the victim cache line.

14. The data processing system of claim 13, wherein the second lower level cache includes LCO throttling logic that empirically measures an effect of accepting victim cache lines that are specified by LCO commands and that have addresses within the guest LCO address region to obtain the empirical metric.

15. The data processing system of claim 14, wherein the LCO throttling logic empirically measures an effect on cache capacity for castouts from the second upper level cache.

16. The data processing system of claim 15, wherein:

the second lower level cache has a home LCO address region;

wherein the LCO throttling logic empirically measures the effect on cache capacity by comparing hit rates of the second upper level cache in the home and guest LCO address regions.

17. The data processing system of claim 10, wherein said second lower level cache further determines whether acceptance of the victim cache line will adversely impact cache bandwidth.

18. The data processing system of claim 10, wherein the second lower level cache further comprises LCO throttling logic that reduces a probability that the second lower level cache will accept the victim cache line by reducing a number of storage locations in the lower level cache allocable to receive victim cache line via LCO commands.

19. A processing unit for a data processing system having a plurality of processing units and a system memory coupled by an interconnect fabric, wherein each of the plurality of processing units includes a processor core and associated upper and lower level caches, said processing unit comprising:

a processor core;

an upper level cache coupled to the processor core; and

a lower level cache coupled to the upper level cache;

wherein the lower level cache, responsive to receiving on the interconnect fabric an LCO command issued by another lower level cache, the LCO command indicating an address of a victim cache line to be castout from the first lower level cache and indicating that the second lower level cache is an intended destination of the victim cache line, determines whether to accept the victim cache line from the another lower level cache based at least in part on the address of the victim cache line indicated by the LCO command;

wherein the lower level cache, responsive to determining not to accept the victim cache line, provides a coherence response to the LCO command refusing the identified victim cache line, and responsive to determining to accept the victim cache line, updates an entry of the lower level cache corresponding to the identified victim cache line.

20. The processing unit of claim 19, wherein the lower level cache is a victim cache.

21. The processing unit of claim 19, wherein the lower level cache determines if the address of the victim cache line falls within a guest LCO address region, and if so, accepts the identified victim cache line.

22. The processing unit of claim 21, wherein the lower level cache, if the address of the victim cache line falls outside the guest LCO address region, determines by reference to an empirical metric of performance of the upper level cache whether to accept the victim cache line.

23. The processing unit of claim 22, wherein the lower level cache includes LCO throttling logic that empirically measures an effect of accepting victim cache lines that are specified by LCO commands and that have addresses within the guest LCO address region to obtain the empirical metric.

24. The processing unit of claim 23, wherein the LCO throttling logic empirically measures an effect on cache capacity for castouts from the upper level cache.

25. The processing unit of claim 24, wherein:

the lower level cache has a home LCO address region;

wherein the LCO throttling logic empirically measures the effect on cache capacity by comparing hit rates of the second upper level cache in the home and guest LCO address regions.

26. The processing unit of claim 19, wherein said lower level cache further determines whether acceptance of the victim cache line will adversely impact cache bandwidth.

27. The processing unit of claim 19, wherein the lower level cache further comprises LCO throttling logic that reduces a probability that the lower level cache will accept the victim cache line by reducing a number of storage locations in the lower level cache allocable to receive victim cache line via LCO commands.