Empirically Based Dynamic Control of Acceptance of Victim Cache Lateral Castouts
First Claim
1. A method of data processing in a data processing system including a plurality of processing units including a first processing unit and a second processing unit coupled by an interconnect fabric, wherein the first processing unit has a first processor core and associated first upper and first lower level caches and the second processing unit has a second processor core and associated second upper and lower level caches, said method comprising:
- receiving on the interconnect fabric at the second lower level cache an LCO command issued by the first lower level cache, wherein the LCO command indicates an address of a victim cache line to be castout from the first lower level cache and indicates that the second lower level cache is an intended destination of the victim cache line;
the second lower level cache determining whether to accept the victim cache line from the first lower level cache based at least in part on the address of the victim cache line indicated by the LCO command;
in response to determining not to accept the victim cache line, providing a coherence response to the LCO command refusing the identified victim cache line; and
in response to determining to accept the victim cache line, updating an entry of the second lower level cache corresponding to the identified victim cache line.
1 Assignment
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Accused Products
Abstract
A second lower level cache receives an LCO command issued by a first lower level cache on an interconnect fabric. The LCO command indicates an address of a victim cache line to be castout from the first lower level cache and indicates that the second lower level cache is an intended destination of the victim cache line. The second lower level cache determines whether to accept the victim cache line from the first lower level cache based at least in part on the address of the victim cache line indicated by the LCO command. In response to determining not to accept the victim cache line, the second lower level cache provides a coherence response to the LCO command refusing the identified victim cache line. In response to determining to accept the victim cache line, the second lower level cache updates an entry corresponding to the identified victim cache line.
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Citations
27 Claims
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1. A method of data processing in a data processing system including a plurality of processing units including a first processing unit and a second processing unit coupled by an interconnect fabric, wherein the first processing unit has a first processor core and associated first upper and first lower level caches and the second processing unit has a second processor core and associated second upper and lower level caches, said method comprising:
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receiving on the interconnect fabric at the second lower level cache an LCO command issued by the first lower level cache, wherein the LCO command indicates an address of a victim cache line to be castout from the first lower level cache and indicates that the second lower level cache is an intended destination of the victim cache line; the second lower level cache determining whether to accept the victim cache line from the first lower level cache based at least in part on the address of the victim cache line indicated by the LCO command; in response to determining not to accept the victim cache line, providing a coherence response to the LCO command refusing the identified victim cache line; and in response to determining to accept the victim cache line, updating an entry of the second lower level cache corresponding to the identified victim cache line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A data processing system, comprising:
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a plurality of processing units including a first processing unit and a second processing unit coupled by an interconnect fabric, wherein the first processing unit has a first processor core and associated first upper and first lower level caches and the second processing unit has a second processor core and associated second upper and lower level caches; wherein the second lower level cache, responsive to receiving on the interconnect fabric an LCO command issued by the first lower level cache, the LCO command indicating an address of a victim cache line to be castout from the first lower level cache and indicating that the second lower level cache is an intended destination of the victim cache line, determines whether to accept the victim cache line from the first lower level cache based at least in part on the address of the victim cache line indicated by the LCO command; wherein the second lower level cache, responsive to determining not to accept the victim cache line, provides a coherence response to the LCO command refusing the identified victim cache line, and responsive to determining to accept the victim cache line, updates an entry of the second lower level cache corresponding to the identified victim cache line. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A processing unit for a data processing system having a plurality of processing units and a system memory coupled by an interconnect fabric, wherein each of the plurality of processing units includes a processor core and associated upper and lower level caches, said processing unit comprising:
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a processor core; an upper level cache coupled to the processor core; and a lower level cache coupled to the upper level cache; wherein the lower level cache, responsive to receiving on the interconnect fabric an LCO command issued by another lower level cache, the LCO command indicating an address of a victim cache line to be castout from the first lower level cache and indicating that the second lower level cache is an intended destination of the victim cache line, determines whether to accept the victim cache line from the another lower level cache based at least in part on the address of the victim cache line indicated by the LCO command; wherein the lower level cache, responsive to determining not to accept the victim cache line, provides a coherence response to the LCO command refusing the identified victim cache line, and responsive to determining to accept the victim cache line, updates an entry of the lower level cache corresponding to the identified victim cache line. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27)
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Specification