Memory Controllers, Methods, and Systems Supporting Multiple Memory Modes

• US 20100262790A1
• Filed: 06/22/2010
• Published: 10/14/2010
• Est. Priority Date: 04/12/2007
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Perego, Richard E., Ware, Frederick A.
• Granted Patent: US 8,261,039 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM

Abstract

A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

Claims

1. A memory controller supporting at least two different modes of interaction with a first memory, the first memory having two sections of memory cells, the memory controller comprising:

a register to indicate mode; and

circuitry to direct memory transaction requests over a first request port to access both sections in the first mode, and to direct memory transaction requests over one of the first request port and a second request port to access a respective one of the two sections in the second mode.

2. The memory controller of claim 1, where the memory controller is to program the first memory to, in the first mode, service memory transaction requests sent via the first request port using both sections and in the second mode, to service memory transaction requests sent via the first and second request ports using respective ones of the two sections.

3. The memory controller of claim 1, where the memory controller has four request ports, including the first request port and the second request port and, for each request port, an associated data port.

4. The memory controller of claim 3, where each of the four request ports is to transmit transaction requests over one or more differential, serial links.

5. The memory controller of claim 3, where the memory controller supports at least three different modes, including the first mode and the second mode, where the first memory has four sections of memory cells, and where the circuitry is further to direct memory transaction requests over a first request port to access all four sections in the first mode, to direct memory transactions over one of the first request port and the second request port to access a respective subset of two of the four sections in the second mode, and to direct memory transactions over one of the first request port, the second request port, a third request port and a fourth request port to access a respective one of the four sections in the third mode.

6. The memory controller of claim 1, where in the first mode the memory controller further supports interaction with a second memory, and where:

the circuitry is to direct memory transaction requests over the first request port to access both sections of the first memory in the first mode, and over the second request port to access the second memory in the first mode, and to direct memory transactions over one of the first request port and the second request port to access a respective one of the two sections of the first memory in the second mode; and

a data granularity associated with the memory transaction requests in the second mode is twice a data granularity associated with memory transaction requests in the first mode.

7. The memory controller of claim 6, where the memory controller is to, at least when the second memory is present and the memory controller is in the second mode, stagger in time transaction requests sent to the second memory relative to transaction requests sent to the first memory.

8. The memory controller of claim 1, where, when in the first mode the controller accesses multiple sections of memory, the access is simultaneous to both sections.

9. The memory controller of claim 1, where the first memory is a memory module, the memory controller to communicate with the memory module via the first request port in point-to-point fashion, the memory device to route communications from the memory controller to one or more memory devices resident on the first memory module.

10. The memory controller of claim 1, embodied in an integrated circuit memory device.

11. The memory controller of claim 1, where the memory controller has a data port associated with each request port and is to transmit transaction requests over each request port and associated data port using an identical bit rate.

12. The memory controller of claim 1, further comprising a first data port to couple the controller with the first memory using a point-to-point link and a second data port to couple the controller with one of the first memory or a second memory using a point-to-point link, the controller to communicate over the second data port with either the first memory or the second memory depending on mode.

13. The memory controller of claim 12, where the controller is to communicate in point-to-point fashion over the second request port to the first memory in the second mode via a continuity module.

14. The memory controller of claim 1, where the first memory is an integrated circuit device, and where the memory controller is to adjust a control register within the integrated circuit device upon a change in mode.

15. The memory controller of claim 1, where in the first mode the first memory uses a specific word size for memory transaction requests sent via either the first or second request port and in the second mode uses twice the specific word size for memory transaction requests sent via the first request port.

16. A method of operation in a memory system having a memory controller and a first memory, the method comprising:

determining mode, selected from a first mode, in which two sets of request lines are used for memory access in the first memory, each set of request lines being used to access a respective one of first and second sections of memory cells, and a second mode, in which only one of the two sets of request lines is used for memory access of both sections; and

sending memory transaction requests in the first mode via one of the first and second sets of request lines depending on whether each memory transaction request is to access the first section or the second section.

17. The method of claim 16, further comprising:

in the second mode, programming the first memory to service memory transaction requests sent via the first and second sets of request lines using the first and second sections of memory cells, respectively; and

in the first mode, programming the first memory to service memory transaction requests sent via the first set of request lines using the first and second sections of memory cells.

18. The method of claim 16, further comprising:

in the second mode, programming the first memory to service memory transaction requests sent via the first and second sets of request lines using the first and second sections of memory cells, respectively; and

in the first mode, programming the first memory to service each memory transaction request sent via the first set of request lines using both of the first and second sections of memory cells;

where the memory transaction requests are serviced using a first data granularity in the second mode, and half of the first data granularity in the first mode.

19. The method of claim 16, where in the first mode, a second memory is to service memory transactions sent via the second set of request lines.

20. The method of claim 19, further comprising, at least when the second memory is present and the second mode is determined, staggering in time transaction requests sent to the second memory relative to transaction requests sent to the first memory.

21. The method of claim 16, where the first memory is an integrated circuit device, the method further comprising adjusting a control register within the integrated circuit device upon a change in mode.

22. The method of claim 16, where in the first mode the first memory uses a specific word size for memory transaction requests sent via either the first or the second request set of request lines and in the second mode uses twice the specific word size for memory transaction requests sent via the first set of request lines.

23. The method of claim 16, where in the first mode the first memory uses a specific word size for memory transaction requests sent via either the first or the second set of request lines and in the second mode also uses the specific word size for memory transaction requests sent via the first set of request lines, to utilize a constant granularity of data transactions irrespective of the mode.

24. The method of claim 16, where the first memory is a memory module having one or more memory devices arranged in a fly-by configuration, the method further comprising transmitting memory transaction requests to the memory module, and servicing the request using at least one memory device on the memory module.

25. The method of claim 16, embodied in a memory controller.

26. A memory system, comprising:

a memory controller;

a first memory having two sections of memory cells; and

first and second request links;

where the memory system supports two modes, including

a first mode where the controller is to communicate memory transaction requests to individual sections of the first memory via a respective one of the first request link and the second request link; and

a second mode where the controller is to communicate memory transaction requests to the first memory over the first request link for both of the sections.

27. The memory system of claim 26, where in the second mode, the controller is to communicate memory transaction requests such that each transaction request simultaneously accesses both sections of memory, such that data granularity in the second mode is half of data granularity in the first mode.

28. The memory system of claim 26, where in the second mode, the controller is to communicate memory transaction requests such that each transaction request accesses only one of the two sections, such that data granularity in the second mode is equal to data granularity in the first mode.

29. The memory system of claim 26, where the first memory includes a first group of one or more integrated circuit memory devices arranged in a fly-by configuration.

30. The memory system of claim 29, where the first group is part of a memory module having a primary interface, each request link coupling the memory module with the memory controller configured as a point-to-point link between the primary interface and the memory controller, and distributed between the primary interface and the group of one or more memory devices associated with the module in a multi-drop topology.

31. The memory system of claim 26, where the memory controller and each memory is embodied in a respective, discrete integrated circuit device.

32. The memory system of claim 26, where the memory controller has four request ports, including the first request port and the second request port and, for each request port, an associated data port.

33. The memory system of claim 32, where each of the four request ports is to transmit transaction requests over one or more differential, serial links.

34. The memory system of claim 32, where the memory controller supports at least three different modes, including the first mode and the second mode, and further a third mode, where the first memory has four sections of memory cells, and where the memory controller is further to direct memory transaction requests over a first request port to access all four sections in the first mode, to direct memory transactions over one of the first request port and the second request port to access a respective subset of two of the four sections in the second mode, and to direct memory transactions over one of the first request port, the second request port, a third request port and a fourth request port to access a respective one of the four sections in the third mode.

35. The memory system of claim 26, where the memory controller has a data port associated with each request port and is to transmit transaction requests over each request port and the associated data port using an identical bit rate.

36. The memory system of claim 26, further comprising a first data port to couple the controller with the first memory using a point-to-point link and a second data port configured to couple the controller with one of the first memory or a second memory as a point-to-point link, the controller to communicate over the second data port with either the first memory or the second memory depending on mode.

37. The memory system of claim 36, where the memory controller is to, at least when the second memory is present and the memory controller is in the second mode, stagger in time the second transaction requests relative to the first transaction requests.

38. The memory system of claim 36, where the second request link is to couple the controller with the first memory through a continuity module that is selectively removed to install the second memory.

39. The memory system of claim 38, where the first memory is a memory module, the memory controller to communicate with the memory module via the first request port in point-to-point fashion, the continuity module to route communications from the memory controller to one or more memory devices resident on the first memory module.

40. The memory system of claim 26, where the first memory is an integrated circuit device, and where the memory controller is to adjust a control register within the integrated circuit device upon a change in mode.

41. An apparatus, comprising:

means for determining mode, selected from a first mode, in which two sets of request lines are used for memory access in the first memory, each set of request lines being used to access a respective one of first and second sections of memory cells, and a second mode, in which only one of the two sets of request lines is used for memory access of both sections; and

means for sending memory transaction requests in the first mode via one of the first and second sets of request lines depending on whether each memory transaction request is to access the first section or the second section.

42. A memory controller supporting at least two different modes of interaction with a first memory, the first memory having two sections of memory cells, the memory controller comprising:

a register to indicate mode;

two request ports to communicate with the first memory; and

circuitry to direct memory transaction requests over only one of the two request ports to access both sections in the first mode, and to direct memory transactions over each of the two request ports to access a respective one of the two sections in the second mode.

43. The memory controller of claim 42, where the controller is to programmatically assign one of the two request ports for communicating with the first memory in the first mode by programming a configuration register in the memory device.