SOFTWARE REFRESHED MEMORY DEVICE AND METHOD

• US 20100262791A1
• Filed: 06/28/2010
• Published: 10/14/2010
• Est. Priority Date: 08/29/2002
• Status: Active Grant

• Current Assignee: Ovonyx Memory Technology, LLC
• Original Assignee: Terry L. Gilton
• Inventors: Gilton, Terry L.
• Granted Patent: US 7,944,768 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40603 Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 5/005 Circuit means for protection against loss of information of semiconductor storage devices

Abstract

A software refreshed memory device comprises a plurality of memory cells that must be periodically refreshed to avoid losing data. Preferably, the memory cells can avoid losing data even though the time interval between successive memory refresh operations is relatively long, as compared to the time interval between successive memory refresh operations in a conventional volatile memory device, such as a DRAM. A processor can perform periodic memory refresh operations by executing a set of memory refresh instructions implemented in software, rather than in hardware. Accordingly, the memory device can advantageously be simplified, because the need for memory refresh circuitry and for a unique refresh control signal are advantageously eliminated. Moreover, the processor executing the memory refresh instructions can typically perform more sophisticated algorithms, as compared to memory refresh circuitry implemented in hardware, for determining when to perform a memory refresh operation. For example, the processor can determine whether each individual memory cell needs to be refreshed, thereby advantageously avoiding performing unnecessary refresh operations on memory cells that do not need to be refreshed.

Claims

1-23. -23. (canceled)

24. A method of refreshing a memory cell, the method comprising:

determining whether a memory refresh operation is complete;

if the memory refresh operation is not yet complete, determining whether system resources are available to refresh a memory cell;

if the memory refresh operation is not yet complete and system resources are available to refresh the memory cell, refreshing the memory cell; and

if the memory operation is not yet complete and system resources are not available to refresh the memory cell, forcing at least some of the system resources to become available to refresh the memory cell.

25. The method of claim 24, further comprising starting a timer.

26. The method of claim 24, wherein refreshing the memory cell comprises refreshing a memory cell at an address corresponding to a current value of a counter, and further comprising incrementing the counter after refreshing the memory cell.

27. The method of claim 26, further comprising resetting the counter if the memory refresh operation is complete.

28. The method of claim 24, wherein determining whether a memory refresh operation is complete comprises determining whether each memory cell in a memory array has been refreshed.

29. The method of claim 24, wherein determining whether a memory refresh operation is complete comprises determining whether each memory cell in a particular block of memory has been refreshed.

30. The method of claim 25, wherein forcing at least some of the system resources to become available to refresh the memory cell comprises forcing at least some of the system resources to become available to refresh the memory cell responsive to determining that the timer has exceeded a maximum wait time.

31. The method of claim 30, wherein the maximum wait time comprises the maximum time that the memory cell can retain an assigned state.

32. The method of claim 30, wherein the maximum wait time corresponds to the maximum time that a processor can wait before it forces at least some of the system resources to become available to refresh remaining memory cells.

33. The method of claim 32, wherein the remaining memory cells comprise the remaining memory cells in a memory array being refreshed.

34. The method of claim 32, wherein the remaining memory cells comprise the remaining memory cells in a block of memory being refreshed.

35. The method of claim 30, further comprises monitoring whether system resources have become available to refresh the memory cell if the timer has not exceeded the maximum wait time.

36. The method of claim 24, further comprising repeating the method periodically.

37. The method of claim 24, wherein the memory cell comprises a variable resistance memory cell.

38. A memory device comprising:

a plurality of variable resistance memory cells; and

a processor coupled to the plurality of variable resistance memory cells, said processor configured to determine whether a memory refresh operation is complete;

if the memory refresh operation is not yet complete, determine whether system resources are available to refresh a memory cell;

if the memory refresh operation is not yet complete and system resources are available to refresh the memory cell, refresh the memory cell; and

if the memory operation is not yet complete and system resources are not available to refresh the memory cell, force at least some of the system resources to become available to refresh the memory cell.

39. The memory device of claim 38, wherein the variable resistance memory cells comprise programmable conductor random access memory cells.

40. The memory device of claim 38, wherein the processor monitors whether system resources have become available to refresh the memory cell if the timer has not exceeded the maximum wait time.

41. The memory device of claim 38, wherein when the processor forces at least some of the system resources to become available to refresh the memory cell, the processor forces at least some of the system resources to become available to refresh the memory cell responsive to determining that the timer has exceeded a maximum wait time.

42. The memory device of claim 41, wherein the maximum wait time comprises the maximum time that each of the plurality of variable resistance memory cells can retain an assigned state.

43. The method of claim 41, wherein the maximum wait time corresponds to the maximum time that a processor can wait before it forces at least some of the system resources to become available to refresh remaining memory cells.