RELIABILITY, AVAILABILITY, AND SERVICEABILITY IN A MEMORY DEVICE
First Claim
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1. A memory device comprising:
- a memory core having a first portion to store data bits and a second portion to store error correction code (ECC) bits (stored ECC bits) corresponding to the data bits; and
error correction logic on the same die as the memory core, the error correction logic including ECC computation logic to compute ECC bits (computed ECC bits) corresponding to the data bits.
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Abstract
Embodiments of the invention are generally directed to improving the reliability, availability, and serviceability of a memory device. In some embodiments, a memory device includes a memory core having a first portion to store data bits and a second portion to store error correction code (ECC) bits corresponding to the data bits. The memory device may also include error correction logic on the same die as the memory core. In some embodiments, the error correction logic enables the memory device to compute ECC bits and to compare the stored ECC bits with the computed ECC bits.
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Citations
22 Claims
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1. A memory device comprising:
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a memory core having a first portion to store data bits and a second portion to store error correction code (ECC) bits (stored ECC bits) corresponding to the data bits; and error correction logic on the same die as the memory core, the error correction logic including ECC computation logic to compute ECC bits (computed ECC bits) corresponding to the data bits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method comprising:
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reading data bits from a first portion of a memory core; reading stored error correction code (ECC) bits from a second portion of the memory core; generating computed ECC bits using ECC computation logic, wherein the memory core and the ECC computation logic are on a common integrated circuit; and comparing the stored ECC bits with the computed ECC bits to determine whether the stored ECC bits match the computed ECC bits. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A system comprising:
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a dynamic random access memory (DRAM) device including a split bank pair of memory banks including a first memory bank and a second memory bank, wherein data bits are to be stored in the first memory bank and corresponding error correction code (ECC) bits (stored ECC bits) are to be stored in the second memory bank, if the DRAM device is in an error check mode, and error correction logic on the same die as the split bank pair, the error correction logic including ECC generation logic to compute ECC bits (computed ECC bits) corresponding to the data bits; and a requestor coupled with the DRAM device. - View Dependent Claims (18, 19, 20, 21, 22)
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Specification