RELIABILITY, AVAILABILITY, AND SERVICEABILITY IN A MEMORY DEVICE

• US 20100262889A1
• Filed: 06/28/2010
• Published: 10/14/2010
• Est. Priority Date: 06/30/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: BAINS, KULJIT S.
• Granted Patent: US 8,806,298 B2
• Time in Patent Office: Days
• US Class Current: 714/758
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence

Abstract

Embodiments of the invention are generally directed to improving the reliability, availability, and serviceability of a memory device. In some embodiments, a memory device includes a memory core having a first portion to store data bits and a second portion to store error correction code (ECC) bits corresponding to the data bits. The memory device may also include error correction logic on the same die as the memory core. In some embodiments, the error correction logic enables the memory device to compute ECC bits and to compare the stored ECC bits with the computed ECC bits.

Claims

1. A memory device comprising:

a memory core having a first portion to store data bits and a second portion to store error correction code (ECC) bits (stored ECC bits) corresponding to the data bits; and

error correction logic on the same die as the memory core, the error correction logic including ECC computation logic to compute ECC bits (computed ECC bits) corresponding to the data bits.

2. The memory device of claim 1, wherein the memory core includes a split bank pair of memory banks having a first memory bank corresponding to the first portion and a second memory bank corresponding to the second portion.

3. The memory device of claim 1, wherein the error correction logic further comprises:

ECC correction logic to correct an error in the data bits.

4. The memory device of claim 3, wherein the error correction logic further comprises:

a comparator to compare the stored ECC bits with the computed ECC bits.

5. The memory device of claim 4, wherein the error correction logic further comprises:

cyclic redundancy code (CRC) generation logic to generate CRC bits corresponding to the data bits.

6. The memory device of claim 5, wherein the error correction logic further comprises:

framing logic to send the CRC bits and the data bits to a requester.

7. The memory device of claim 1, wherein the memory device comprises a dynamic random access memory (DRAM) device.

8. The memory device of claim 1, wherein the memory device is capable of operating in an error check mode and a non-error check mode.

9. The memory device of claim 8, wherein the memory device further comprises:

mapping logic to map the stored ECC bits to the second portion of the memory core.

10. A method comprising:

reading data bits from a first portion of a memory core;

reading stored error correction code (ECC) bits from a second portion of the memory core;

generating computed ECC bits using ECC computation logic, wherein the memory core and the ECC computation logic are on a common integrated circuit; and

comparing the stored ECC bits with the computed ECC bits to determine whether the stored ECC bits match the computed ECC bits.

11. The method of claim 10, wherein the memory core includes a split bank pair of memory banks having a first memory bank corresponding to the first portion and a second memory bank corresponding to the second portion.

12. The method of claim 10, further comprising:

computing cyclic redundancy code (CRC) bits corresponding to the data bits, if the stored ECC bits match the computed ECC bits; and

sending the CRC bits and the data bits to a requester.

13. The method of claim 10, further comprising:

determining whether the data bits contain a single bit error, if the stored ECC bits do not match the computed ECC bits; and

if the data bits contain a single bit error, then correcting the single bit error using ECC correction logic, wherein the ECC correction logic and the memory core are on a common integrated circuit.

14. The method of claim 13, further comprising:

sending the CRC bits and the data bits to a requester, subsequent to correcting the single bit error.

15. The method of claim 14, wherein sending the CRC bits and the data bits to the requester comprises:

framing the data bits in a read data frame;

appending the CRC bits to the read data frame; and

sending the read data frame to the requester.

16. The method of claim 13, further comprising:

reporting an error to a requester, if the data bits do not contain a single bit error.

17. A system comprising:

a dynamic random access memory (DRAM) device including

a split bank pair of memory banks including a first memory bank and a second memory bank, wherein data bits are to be stored in the first memory bank and corresponding error correction code (ECC) bits (stored ECC bits) are to be stored in the second memory bank, if the DRAM device is in an error check mode, and

error correction logic on the same die as the split bank pair, the error correction logic including ECC generation logic to compute ECC bits (computed ECC bits) corresponding to the data bits; and

a requestor coupled with the DRAM device.

18. The system of claim 17, wherein the error correction logic further comprises:

ECC correction logic to correct an error in the data bits.

19. The system of claim 18, wherein the error correction logic further comprises:

a comparator to compare the stored ECC bits with the computed ECC bits.

20. The system of claim 17, wherein the error correction logic further comprises:

cyclic redundancy code (CRC) generation logic to generate CRC bits corresponding to the data bits.

21. The system of claim 17, wherein error correction logic further comprises:

framing logic to send the CRC bits and the data bits to a requester.

22. The system of claim 17, wherein the DRAM device further includes:

mapping logic to map the stored ECC bits to the second memory bank.