MULTI CORE SYSTEM, VEHICULAR ELECTRONIC CONTROL UNIT, AND TASK SWITCHING METHOD

• US 20100262971A1
• Filed: 02/23/2009
• Published: 10/14/2010
• Est. Priority Date: 07/22/2008
• Status: Active Grant

• Current Assignee: Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Original Assignee: Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Inventors: Yamada, Kazumi
• Granted Patent: US 8,856,196 B2
• Time in Patent Office: Days
• US Class Current: 718/104
• CPC Class Codes: G06F 11/004 Error avoidance G06F11/07 and subgroups take precedence
• CPC Class Codes: G06F 11/1641 where the comparison is not performed by the redundant processing components
• CPC Class Codes: G06F 2209/508 Monitor
• CPC Class Codes: G06F 9/505 considering the load
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multi core system for allocating a task generated from a control system program to an appropriate CPU core and executing the task includes a trial-execution instructing part configured to cause a second CPU core to trial-execute a task which a first CPU core executes before the multi core system transfers the task from the first CPU core to the second CPU core and causes the second CPU core to execute the task, a determining part configured to determine whether an execution result by the first CPU core matches an execution result by the second CPU core, and an allocation fixing part configured to fix the second CPU core as the appropriate CPU core to which the task is allocated if the determining part determines that the execution result by the first CPU core matches the execution result by the second CPU core.

Claims

1. A multi core system for allocating a task generated from a control system program to a CPU core and executing the task, comprising:

a trial-execution instructing part configured to cause a second CPU core to trial-execute a task which a first CPU core executes before the multi core system transfers the task from the first CPU core to the second CPU core and causes the second CPU core to execute the task;

a determining part configured to determine whether the execution result by the first CPU core matches the trial-execution result by the second CPU core; and

an allocation fixing part configured to fix the second CPU core as the CPU core to which the task is allocated if the determining part determines that the execution result by the first CPU core matches the trial-execution result by the second CPU core.

2. A multi core system according to claim 1, wherein:

the trial-execution instructing part is configured to cause two or more second CPU cores to trial-execute the task,

the determining part is configured to compare the execution result by the first CPU core and each of the trial-execution results by the two or more second CPU cores, and

the allocation fixing part is configured to fix a CPU core having the earliest trial-execution result among the two or more second CPU cores as the CPU core to which the task is allocated, wherein the earliest trial-execution result matches the execution result by the first CPU core.

3. A multi core system according to claim 1, further comprising a processing load detecting part configured to detect a processing load of the first CPU core,

wherein:

the trial-execution instructing part is configured to cause the second CPU core to trial-execute the task if the processing load detecting part detects that a processing load of the first CPU core has become high or that there is a possibility that a processing load of the first CPU core will become high.

4. A multi core system according to claim 1 wherein:

the trial-execution instructing part is configured to cause the first CPU core to trial-execute the task if the first CPU core is not executing the task.

5. A multi core system according to claim 1, further comprising a processing load detecting part configured to detect processing loads of the first CPU core and the second CPU core,

wherein:

the trial-execution instructing part is configured to cause the first CPU core and the second CPU core to trial-execute the task which the first CPU core or the second CPU core having a higher processing load have been executing if the processing load detecting part detects an imbalance or the possibility of an imbalance between the processing load of the first CPU core and the processing load of the second CPU core.

6. A multi core system according to claim 1, wherein:

the determining part is configured to determine that the execution result by the first CPU core matches the trial-execution result by the second CPU core if a difference between the execution result by the first CPU core and the trial-execution result by the second CPU core is within a predetermined range.

7. A multi core system according to claim 6, wherein:

the difference is predetermined depending on the task.

8. A multi core system according to claim 1, wherein:

the determining part is configured to, in the event the execution result by the first CPU core does not match the trial-execution result by the second CPU core, repeat determining until the execution result by the first CPU core matches the trial-execution result by the second CPU core within a predetermined standby time.

9. A multi core system according to claim 1, further comprising a priority table configured to register the CPU core to which the task is allocated in relation to the task,

wherein:

the trial-execution instructing part is configured to refer to the priority table to determine a CPU for core trial-executing the task.

10. A multi core system according to claim 1, wherein:

comprising a processing load detecting part configured to detect processing loads of CPU cores,

a task which the trial-execution instructing part causes the second CPU core to trial-execute is a task which the first CPU core is executing when the processing load detecting part has detected that a processing load of the first CPU core has become greater than a first threshold value or the processing load detecting part has detected that there is a possibility that a processing load of the first CPU core will become greater than the first threshold value, or when the processing load detecting part has detected an imbalance or the possibility of an imbalance among processing loads of a plurality of CPU cores.

11. A multi core system according to claim 10, wherein:

the first CPU core is configured to output to a controlled object an execution result of the task which the first CPU core is executing when the processing load detecting part has detected that a processing load of the first CPU core has become greater than a first threshold value or the processing load detecting part has detected that there is a possibility that a processing load of the first CPU core will become greater than the first threshold value, or when the processing load detecting part has detected an imbalance or the possibility of an imbalance among processing loads of a plurality of CPU cores.

12. A multi core system according to claim 3, wherein:

the processing load detecting part is configured to detect that the processing load of the first CPU core is greater than a first threshold value if at least one of conditions is met, the conditions being that a CPU core usage rate representing a rate of an execution time period of the task with respect to a predetermined time period is greater than a threshold value T_R1, and that the number of tasks in standby is greater than a threshold value T_N1, and

the processing load detecting part is configured to detect that the processing load of the first CPU core will become greater than the first threshold value if at least one of conditions is met, the conditions being that an increasing rate of the CPU core usage rate is greater than a threshold value T_dR1, and that an increasing rate of the number of tasks in standby is greater than a threshold value T_dN1.

13. A multi core system according to claim 3, wherein:

the processing load detecting part is configured to detect that the processing load of the first CPU core is greater than a threshold value if a status value representing a state of a vehicle is greater than a threshold value T_S, and

the processing load detecting part is configured to detect that the processing load of the first CPU core will become greater than the threshold value if an increasing rate of the status value representing a state of a vehicle is greater than a threshold value T_dS.

14. A multi core system according to claim 5, wherein:

the processing load detecting part is configured to detect the imbalance between the processing load of the first CPU core and the processing load of the second CPU core if at least one of conditions is met, the conditions being that a difference between a CPU core usage rate of the first CPU core representing a rate of an execution time period of the task with respect to a predetermined time period and a CPU core usage rate of the second CPU core is greater than a threshold value T_R12, and that a difference between the number of tasks waiting for an execution by the first CPU core and the number of tasks waiting for an execution by the second CPU core is greater than a threshold value T_R12, and

the processing load detecting part is configured to detect the possibility of an imbalance between the processing load of the first CPU core and the processing load of the second CPU core if at least one of conditions is met, the conditions being that an increasing rate of the difference between the CPU usage rate of the first CPU core and the CPU usage rate of the second CPU core is greater than a threshold value T_dR12, and that an increasing rate of the difference between the number of tasks waiting for an execution by the first CPU core and the number of tasks waiting for an execution by the second CPU core is greater than a threshold value T_dN12.

15. A multi core system according to claim 3, wherein:

comprising a processing load detecting part configured to detect a processing load of the second CPU core,

the trial-execution instructing part is configured to cause the first CPU core and the second CPU core to trial-execute the task which the second CPU core executes if the processing load detecting part detects that the processing load of the second CPU core is lower than a threshold value,

the determining part is configured to determine whether the trial-execution result by the first CPU core matches the trial-execution result by the second CPU core,

the multi core system is configured to switch a CPU core for executing the task from the second CPU core to the first CPU core, and stop the second CPU core if the determining part determines that the trial-execution result by the first CPU core matches the trial-execution result by the second CPU core.

16. A multi core system according to claim 1, in combination with a control system program, wherein:

the control system program is a program utilizing a previous execution result for an execution of a next task.

17. A vehicular electronic control unit, comprising:

the multi core system according to claim 1;

a storing part configured to store the control system program; and

an interface connected to an actuator.

18. A task switching method of a multi core system for allocating a task generated from a control system program to a CPU core and executing the task, comprising:

a trial-execution instructing part causes a first CPU core and a second CPU core to trial-execute a task which a first CPU core executes before the multi core system transfers the task from the first CPU core to the second CPU core and causes the second CPU core to execute the task;

a determining part determines whether trial-execution result by the first CPU core matches trial-execution result by the second CPU core; and

an allocation fixing part fixes the second CPU core as the CPU core to which the task is allocated if the determining part determines that the trial-execution result by the first CPU core matches the trial-execution result by the second CPU core.