BASE STRUCTURE FOR III-V SEMICONDUCTOR DEVICES ON GROUP IV SUBSTRATES AND METHOD OF FABRICATION THEREOF

• US 20100263707A1
• Filed: 04/16/2010
• Published: 10/21/2010
• Est. Priority Date: 04/17/2009
• Status: Abandoned Application

• Current Assignee: Arise Technologies Corporation (Salamon Group, Inc.)
• Original Assignee: Arise Technologies Corporation (Salamon Group, Inc.)
• Inventors: Preston, John Stewart, Cheong, Dan Daeweon, Robinson, Bradley Joseph, Komarnycky, Nicholas, Kleiman, Rafael Nathan, Peter, Manuela
• Application Number:
  US12/762,256
• Publication Number:
  US 20100263707A1
• Time in Patent Office: Days
• US Class Current: 136/244
• CPC Class Codes: C30B 23/02 Epitaxial-layer growth
• CPC Class Codes: C30B 23/025 characterised by the substrate
• CPC Class Codes: C30B 25/183 being provided with a buffer layer, e.g. a lattice matching layer
• CPC Class Codes: C30B 29/40 AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
• CPC Class Codes: C30B 29/42 Gallium arsenide
• CPC Class Codes: C30B 29/44 Gallium phosphide
• CPC Class Codes: H01L 31/1852 comprising a growth substrate not being an AIIIBV compound
• CPC Class Codes: Y02E 10/544 Solar cells from Group III-V materials

Abstract

The structure presented herein provides a base structure for semiconductor devices, in particular for III-V semiconductor devices or for a combination of III-V and Group IV semiconductor devices. The fabrication method for a base substrate comprises a buffer layer, a nucleation layer, a Group IV substrate and possibly a dopant layer. There are, in a general aspect, two growth steps: firstly the growth of a lattice-matched III-V material on a Group IV substrate, followed by secondly the growth of a lattice-mismatched III-V layer. The first layer, called the nucleation layer, is lattice-matched or closely lattice-matched to the Group IV substrate while the following layer, the buffer layer, deposited on top of the nucleation layer, is lattice-mismatched to the nucleation layer. The nucleation layer can further be used as a dopant source to the Group IV substrate, creating a p-n junction in the substrate through diffusion. Alternatively a separate dopant layer may be introduced.

Claims

1. A base structure for fabricating semiconductor devices comprising:

(a) a Group IV semiconductor substrate;

(b) a nucleation layer deposited on said substrate, said nucleation layer comprising a Group III-V material, wherein said nucleation layer is one of closely lattice matched and lattice matched to said substrate; and

(c) a buffer layer deposited on said nucleation layer, said buffer layer comprising a III-V material, wherein said buffer layer is lattice mismatched to said nucleation layer.

2. The base structure according to claim 1 wherein said substrate comprises one of an intrinsic Group IV semiconductor, a Group IV semiconductor alloy, and a doped Group IV semiconductor.

3. The base structure according to claim 1 wherein said Group IV substrate comprises a specific crystallographic orientation and wherein a surface of said substrate comprises an off-axis angle between 0 and 10 degrees.

4. The base structure according to claim 1 wherein said substrate comprises one of silicon and germanium.

5. The base structure according to claim 1 wherein a thickness of said nucleation layer is less than approximately 50 nm.

6. The base structure according to claim 1 wherein said nucleation layer comprises one of a III-P material and a III-P alloy, wherein a Group III component of said III-P material comprises at least one of the elements Al and Ga.

7. The base structure according to claim 1 wherein said nucleation layer comprises one of a III-As material and a III-As alloy, wherein a Group III component of said III-As material comprises at least one of the elements Al or Ga.

8. The base structure according to claim 1 wherein said nucleation layer comprises an element that contributes a dopant to said substrate during a thermal processing step.

9. The base structure according to claim 1 wherein said buffer layer comprises a III-Sb material or alloy, wherein a Group III component of said III-Sb material or alloy comprises one or more elements selected from the group consisting of Al, Ga and In.

10. The base structure according to claim 1 wherein said buffer layer comprises a III-As material or alloy, wherein a Group III component of said III-As material or alloy comprises one or more elements selected from the group consisting of Al, Ga and In.

11. The base structure according to claim 1 further comprising a dopant layer, wherein said dopant layer is formed on said buffer layer.

12. The base structure according to claim 11 wherein said dopant layer is one of lattice matched and closely lattice matched to said buffer layer.

13. The base structure according to claim 11 wherein said dopant layer comprises a material selected from the group consisting III-P, III-P alloys, III-As and III-As alloys.

14. The base structure according to claim 1 further comprising a dopant layer, wherein said dopant layer is provided between said buffer layer and said nucleation layer, wherein said buffer layer is lattice mismatched to said dopant layer, wherein said dopant layer is one of closely lattice matched and lattice matched to said nucleation layer.

15. The base structure according to claim 14 wherein said dopant layer comprises a material selected from the group consisting III-P, III-P alloys, III-As and III-As alloys.

16. The base structure according to claim 11 wherein said substrate comprises an additional dopant, wherein a p-n junction is formed within said substrate following the diffusion of said dopant from said dopant layer into said substrate layer.

17. The base structure according to claim 14 wherein said substrate comprises an additional dopant, wherein a p-n junction is formed within said substrate following the diffusion of said dopant from said dopant layer into said substrate layer.

18. The base structure according to claim 1 further comprising one or more semiconductor device layers formed on an upper surface of said structure.

19. The base structure according to claim 18 wherein said one or more semiconductor device layers comprise a semiconductor material selected from the group consisting of Group III-V materials, Group II-VI materials, and a combination thereof.

20. The base structure according to claim 18 wherein said base structure and said semiconductor device layers comprise a device selected from the group consisting of lasers, detectors, and solar energy conversion devices.

21. The base structure according to claim 18 wherein said substrate layer comprises a p-n junction forming a first solar cell having a first band gap, and wherein said structure further comprises semiconductor device layers formed on an upper surface of said structure;

wherein said semiconductor device layers comprise a second solar cell having a second band gap, wherein said second band gap is larger than said first band gap and said first and said second solar cells form a tandem solar cell device.

22. The base structure according to claim 21 further comprising additional semiconductor device layers provided between said first solar cell and said second solar cell, wherein said additional semiconductor device layers comprise a third solar cell having a band gap between that of said first and second band gaps, and wherein said first, second and third solar cells form a triple junction solar cell device.

23. The base structure according to claim 21 further comprising additional semiconductor device layers provided below said substrate, wherein said additional semiconductor device layers comprise a third solar cell having a band gap less than that of said first and second band gaps, and wherein said first, second and third solar cells form a triple junction solar cell device.

24. A method of fabricating a base structure for forming a semiconductor device, said method comprising the steps of:

providing a Group IV semiconductor substrate;

depositing a nucleation layer on said substrate, said nucleation layer comprising a Group III-V material, wherein said nucleation layer is one of closely lattice matched and lattice matched to said substrate; and

depositing a buffer layer on said nucleation layer, said buffer layer comprising a III-V material, wherein said buffer layer is lattice mismatched to said nucleation layer.

25. The method according to claim 24 wherein a thickness of said nucleation layer is less than approximately 50 nm.

26. The method according to claim 24 wherein said nucleation layer comprises an element that may act as a dopant to said substrate, said method further comprising the step of thermally processing said base structure to cause the transport of said dopant to said substrate.

27. The method according to claim 24 further comprising the step of depositing a dopant layer onto said buffer layer, wherein said dopant layer is one of lattice matched and closely lattice matched to said buffer layer.

28. The method according to claim 24 further comprising the step of depositing a dopant layer onto said nucleation layer prior to said step of depositing said buffer layer, wherein said buffer layer is lattice mismatched to said dopant layer.

29. The method according to claim 27 further comprising the step of thermally processing said base structure to cause the transport of said dopant to said substrate.

30. The method according to claim 28 further comprising the step of thermally processing said base structure to cause the transport of said dopant to said substrate.

31. The method according to claim 24 further comprising the step of forming a semiconductor device by depositing one or more semiconductor device layers onto said buffer layer.

32. The method according to claim 31 wherein said semiconductor device layers are deposited using a process selected from the group consisting of molecular beam epitaxy, chemical vapour deposition and metal organic chemical vapour deposition.