Capacitor Structure in Trench Structures of Semiconductor Devices and Semiconductor Devices Comprising Capacitor Structures of this Type and Methods for Fabricating the Same

• US 20100264456A1
• Filed: 06/30/2010
• Published: 10/21/2010
• Est. Priority Date: 09/13/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Strack, Helmut, Schulze, Hans-Joachim, Mauder, Anton
• Granted Patent: US 8,187,947 B2
• Time in Patent Office: Days
• US Class Current: 257/139
• CPC Class Codes: H01L 28/82 with an enlarged surface, e.g. formed by texturisation
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate

Abstract

A capacitor structure in trench structures of a semiconductor device includes conductive regions made of metallic and/or semiconducting materials. The conducting regions are surrounded by a dielectric and form stacked layers in the trench structure of the semiconductor device.

Claims

1. A capacitor structure, comprising:

a plurality of conductive regions of metallic and/or semiconducting materials and/or conductive metal compounds thereof, the conductive regions being arranged as stacked layers in the trench structure of the semiconductor device; and

a dielectric surrounding the conductive regions;

wherein the capacitor structure is embedded in a weakly doped semiconductor body region of one conduction type, which is arranged on a highly doped substrate of the same or opposite conduction type, the capacitor structure surrounding cells of the weakly doped semiconductor body region and the thickness (T_b) of the weakly doped semiconductor body region being greater than the depth (T_g) of the trench structure, such that a buffer layer comprising weakly doped semiconductor material of one conduction type is arranged between the capacitor structure and the highly doped substrate.

2. The capacitor structure of claim 1, wherein the cells are arranged in plate-like fashion one beside the other alternately with the capacitor structure on the highly doped substrate.

3. The capacitor structure of claim 1, wherein the cells are arranged in pillar-like fashion vertically one beside the other in a manner enveloped by the capacitor structure on the highly doped substrate.

4. A semiconductor device comprising the capacitor structure of claim 1, wherein the semiconductor device comprises a Schottky diode structure.

5. The semiconductor device of claim 4, wherein the capacitor structure for the Schottky diode structure is embedded in a weakly doped semiconductor body region of one conduction type, which is arranged on a highly doped substrate of the same conduction type, the capacitor structure surrounding a plurality of cells of the weakly doped semiconductor body region and top sides of the cells comprising a metal coating of a Schottky contact material, which forms an individual electrode of a Schottky diode, individual electrodes of the cells being electrically connected in parallel to form an overall electrode, and a counterelectrode comprises the highly doped substrate.

6. A semiconductor device comprising the capacitor structure of claim 1, wherein the semiconductor device comprises a high-voltage-resistant PN or NP diode structure.

7. The semiconductor device of claim 6, wherein the capacitor structure is embedded in a weakly doped semiconductor body region of one conduction type, which is arranged on a highly doped substrate of the same conduction type, the capacitor structure surrounding a plurality of cells of the weakly doped semiconductor body region and top side regions of the cells having a medium-doped to highly doped diffusion zone of an opposite conduction type, which is coated with an individual metal electrode, a plurality of individual metal electrodes of the cells being electrically connected in parallel to form an overall electrode and being electrically connected to the capacitor structure on the top side of the semiconductor body region, and a counterelectrode of the high-voltage-resistant PN or NP diode comprises the highly doped substrate.

8. A semiconductor device comprising the capacitor structure of claim 1, wherein the semiconductor device comprises a MOS power transistor structure.

9. The semiconductor device of claim 8, wherein:

the capacitor structure is embedded in a weakly doped semiconductor body region of one conduction type, which is arranged on a highly doped substrate of the same conduction type;

the capacitor structure surrounds a plurality of cells of the weakly doped semiconductor body region and top side regions of the cells have a MOS structure with individual source electrodes and individual gate electrodes;

a medium-doped defect well of an opposite conduction type is arranged in the top side region of the cells, which forms a gate channel region towards an edge region of the cells;

a highly doped defect island of the same conduction type as the weakly doped semiconductor body region of the cells is arranged within the defect well, the defect island comprising an individual source electrode and individual source electrodes of the cells being electrically connected in parallel to form a common source electrode and being electrically connected to the capacitor structure;

the gate channel region is covered by a gate oxide and has an individual gate electrode, individual gate electrodes of the cells being connected together to form a common gate electrode above the top side of the weakly doped semiconductor body region; and

the highly doped substrate comprises, on its underside, a metal coating as a large-area drain electrode.

10. A semiconductor device comprising the capacitor structure of claim 1, wherein the semiconductor device includes an IGBT power transistor structure.

11. The semiconductor device of claim 11, wherein:

the capacitor structure is embedded in a weakly doped semiconductor body region of one conduction type, which is arranged on a highly doped substrate of the opposite conduction type;

the capacitor structure surrounds a plurality of cells of the weakly doped semiconductor body region and top side regions of the cells comprise a medium-doped defect well of an opposite conduction type in the top side region of the cells, which forms a gate channel region towards an edge region of the cells;

a highly doped defect island of the same conduction type as the weakly doped semiconductor body region of the cells is arranged within the defect well, the defect island comprising an individual emitter electrode of a bipolar IGBT power transistor with an insulated gate and individual emitter electrodes of the cells being electrically connected in parallel to form a common emitter electrode and being electrically connected to the capacitor structure;

the gate channel region is covered by a gate oxide and comprises an individual gate electrode, individual gate electrodes of the cells being connected together to form a common gate electrode above the top side of the weakly doped semiconductor body region; and

the highly doped substrate comprises a metal coating of a large-area collector electrode on its underside.

12. A method for fabricating a layered capacitor of a semiconductor device, the method comprising:

a) isotropically oxidizing and/or nitriding walls of a trench structure to provide wall protection;

b) anisotropically depositing an oxidizable and/or nitridable conductive material in the trench structure, a deposition rate at the walls being lower than at a bottom of the trench structure at least by at least a factor of two;

c) completely oxidizing and/or nitriding a conductive layer deposited on the walls of the trench structure, while simultaneously oxidizing and/or nitriding a surface region of a conductive layer deposited at the bottom of the trench structure to form a dielectric intermediate layer; and

d) repeating b) and c) until the trench structure is filled to form the layered capacitor.

13. A method for fabricating a layered capacitor of a semiconductor device, the method comprising:

a) isotropically oxidizing and/or nitriding walls of a trench structure to provide wall protection;

b) anisotropically depositing a conductive material in the trench structure, a deposition rate at the walls being lower than at a bottom of the trench structure at least by at least a factor of two;

c) depositing a dielectric material in the trench structure on the conductive material, such that a deposition rate at the walls is lower than at the bottom of the trench structure;

d) producing a selective protective layer on a layer made of the dielectric material at the bottom of the trench structure;

e) etching-back a layer sequence deposited on the walls up to the wall protection; and

f) repeating b) to e) until the trench structure is filled.

14. The method of claim 13, wherein undercuts of the capacitor structure formed by e) are filled by dielectric material.

15. The method of claim 13, wherein deposition parameters during the anisotropic application of conductive and/or dielectric material, for the purpose of setting different layer thicknesses (d_m, d_i), are varied in accordance with a predetermined potential profile in the stacking direction of the layered capacitor.

16. The method of claim 13, wherein etching-back with protection of the layer stack already formed is interposed when overhangs of deposited material are formed at an entrance to the trench structure.

17. The method of claim 13, wherein a) includes oxidizing in an oxygen and/or water vapor atmosphere.

18. The method of claim 13, wherein a) includes performing chemical vapor deposition the isotropic nitriding of the walls of the trench structure.

19. The method of claim 13, wherein b) includes sputtering.

20. The method of claim 13, wherein b) includes a directional vapor deposition.

21. The method of claim 13, wherein b) includes a directional ion beam deposition from a plasma.

22. The method of claims 13, further comprising removing the protective layer via plasma incineration.

23. The method of claim 13, wherein a photolithography method is performed for a masked application of the protective layer.

24. A method for fabricating a layered capacitor for a semiconductor device, the method comprising:

a) isotropically oxidizing and/or nitriding walls of a trench structure of the semiconductor device as wall protection;

b) anisotropically depositing a conductive material in the trench structure, a deposition rate at the walls being lower than at the bottom of the trench structure by at least a factor of two;

c) isotropically etching-back the conductive material until the walls are free of a conductive coating;

d) anisotropically depositing an insulating material in the trench structure, a deposition rate at the walls being lower than at the bottom of the trench structure by at least a factor of two; and

e) repeating b) to d) until the trench structure is filled to form a layered capacitor.