PEAK DETECTION WITH DIGITAL CONVERSION

• US 20100264837A1
• Filed: 04/15/2009
• Published: 10/21/2010
• Est. Priority Date: 04/15/2009
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Zhao, Bin
• Granted Patent: US 8,040,079 B2
• Time in Patent Office: Days
• US Class Current: 315/189
• CPC Class Codes: G01R 19/2506 Arrangements for conditioning or analysing measured signals, e.g. for indicating peak values G01R19/003 takes precedence; Details concerning sampling, digitizing or waveform capturing displaying waveforms G01R13/00; analog sampling G01R19/0053
• CPC Class Codes: H05B 45/38 using boost topology
• CPC Class Codes: H05B 45/46 having LEDs disposed in parallel lines

Abstract

A peak detection/digitization circuit includes a plurality of level detect units, each having a comparator and a flip-flop with a clock input responsive to the output of the comparator. For a detection period, each level detect unit configures a data output signal of the flip-flop to a first data state responsive to a start of the detection period. Further, each level detect unit is configured to enable the comparator responsive to the data output signal having the first data state or a second data state, respectively. While the comparator is enabled during the detection period, the level detect unit configures the data output signal of the flip-flop responsive to a comparison of an input signal to a corresponding reference voltage level by the comparator. The data output signals of the flip-flops of the level detect units at the end of the detection period are used to determine a digital value representative of a peak voltage level of the input signal.

Claims

1. A circuit comprising:

a signal input to receive an input signal;

a digital output to provide a multiple-bit digital value;

a plurality of level detect units, each level detect unit comprising;

a comparator comprising a first input to receive the input signal, a second input to receive a corresponding reference voltage of a plurality of reference voltages, an output to configure a comparator signal based on a comparison of the input signal to the corresponding reference voltage, and an enable input to receive a local enable signal; and

a flip-flop comprising a data input fixed to a predetermined first data state, a clock input coupled to the output of the comparator, a reset input to receive a reset signal, and a first data output to provide a first data signal, the flip-flop to;

responsive to the reset signal having a first reset state, configure the first data signal to a second data state that is the complement of the first data state;

responsive to the comparator signal having a first comparator state while the reset signal has a second reset state, configure the first data signal to the first data state and maintain the first data signal at the first data state until the reset signal is reconfigured to the first reset state; and

responsive to the comparator signal having a second comparator state while the reset signal has the second reset state, maintain a present data state of the first data signal until the reset signal is reconfigured to the first reset state; and

an enable circuit to configure the local enable signal to selectively disable the comparator based at least in part on the first data signal.

2. The circuit of claim 1, wherein the enable circuit is to configure the local enable signal further based on a global enable signal.

3. The circuit of claim 2, wherein the enable circuit comprises an OR logic gate comprising a first input to receive a signal based on the first data signal, a second input to receive a global enable signal, and an output to provide the local enable signal.

4. The circuit of claim 2, further comprising:

a controller to configure the reset signal and the global enable signal based on a reference control signal.

5. The circuit of claim 4, wherein the controller is to configure the global enable signal to a first enable state prior to configuring the reset signal to the first reset state and to configure the global enable signal to a second enable state concurrent with or after configuring the reset signal to the second reset state.

6. The circuit of claim 1, wherein the flip-flop further comprises a second data output to provide a second data signal, the first data signal and the second data signal comprising complementary data signals.

7. The circuit of claim 1, wherein:

the comparator configures the comparator signal to the first comparator state responsive to the input signal having a voltage lower than the corresponding reference voltage and configures the comparator signal to the second comparator state responsive to the input signal having a voltage not lower than the corresponding reference voltage.

8. The circuit of claim 1, wherein:

the comparator configures the comparator signal to the first comparator state responsive to the input signal having a voltage higher than the corresponding reference voltage and configures the comparator signal to the second comparator state responsive to the input signal having a voltage not higher than the corresponding reference voltage.

9. The circuit of claim 1, further comprising:

an output configured to provide an output voltage to a head end of each light emitting diode (LED) string of a plurality of LED strings;

a plurality of tail inputs, each tail input configured to couple to a tail end of a corresponding LED string of the plurality of LED strings; and

a feedback controller coupled to the plurality of tail inputs; and

wherein;

the input signal comprises a minimum tail voltage of the plurality of LED strings;

the multiple-bit digital value comprises a digital code value representative of a minimum voltage of the input signal over a first duration; and

the feedback controller configured to adjust the output voltage for a second duration subsequent to a first duration based on the output voltage and the digital code value.

10. A method comprising:

providing a peak detection/digitization circuit comprising a plurality of level detect units, each level detect unit comprising a comparator and a flip-flop;

receiving an input signal;

for a detection period;

for each level detect unit;

configuring a data output signal of the flip-flop of the level detect unit to a first data state responsive to a start of the detection period;

enabling the comparator responsive to the data output signal having the first data state;

disabling the comparator responsive to the data output signal having a second data state; and

while the comparator of the level detect unit is enabled during the detection period, configuring the data output signal of the flip-flop responsive to a comparison of the input signal to a corresponding reference voltage of a plurality of reference voltages at the comparator; and

latching the data output signals of the flip-flops of the level detect units at an end of the detection period to determine a multiple-bit digital value representative of a peak voltage level of the input signal over the detection period.

11. The method of claim 10, wherein configuring the data output signal of the flip-flop responsive to the comparison of the input signal to the corresponding reference voltage comprises:

configuring the data output signal of the flip-flop to the first data state responsive to the comparison indicating a voltage of the input signal is higher than the corresponding reference voltage; and

configuring the data output signal of the flip-flop to the second data state responsive to the comparison indicating the voltage of the input signal is not higher than the corresponding reference voltage.

12. The method of claim 10, wherein configuring the data output signal of the flip-flop responsive to the comparison of the input signal to the corresponding reference voltage comprises:

configuring the data output signal of the flip-flop to the first data state responsive to the comparison indicating a voltage of the input signal is lower than the corresponding reference voltage; and

configuring the data output signal of the flip-flop to the second data state responsive to the comparison indicating the voltage of the input signal is not lower than the corresponding reference voltage.

13. The method of claim 10, further comprising:

for each level detect unit;

enabling the comparator of the level detect unit responsive to a global enable signal having a first enable state; and

wherein disabling the comparator comprises disabling the comparator responsive to both the data output signal having the second data output state and the global enable signal having a second enable state.

14. The method of claim 13, further comprising:

configuring the global enable signal to the second enable state concurrent with the start of the detection period; and

configuring the global enable signal to the first enable state prior to the start of the detection period.

15. The method of claim 10, further comprising:

providing an output voltage to a head end of each light emitting diode (LED) string of a plurality of LED strings, wherein the input signal comprises a minimum tail voltage of the plurality of LED strings and the multiple-bit digital value represents a minimum tail voltage of the plurality of LED strings over the detection period; and

adjusting the output voltage for another period following the detection period based on the multiple-bit digital value.

16. A circuit comprising:

an output configured to provide an output voltage to a head end of each light emitting diode (LED) string of a plurality of LED strings;

a plurality of tail inputs, each tail input configured to couple to a tail end of a corresponding LED string of the plurality of LED strings; and

a feedback controller coupled to the plurality of tail inputs and comprising;

a peak detection/digitization circuit configured to determine a digital code value representative of a minimum tail voltage of at least one of the plurality of LED strings over a first duration; and

the feedback controller configured to adjust the output voltage for a second duration subsequent to the first duration based on the output voltage and the digital code value; and

wherein the peak detection/digitization circuit comprises;

a signal input to receive the minimum tail voltage;

a digital output to provide the digital code value;

a plurality of level detect units, each level detect unit comprising;

a comparator comprising a first input to receive the analog signal, a second input to receive a corresponding reference voltage of a plurality of reference voltages, an output to configure a comparator signal based on a comparison of the analog signal to the corresponding reference voltage, and an enable input to receive a local enable signal; and

a flip-flop comprising a data input fixed to a predetermined first data state, a clock input coupled to the output of the comparator, a reset input to receive a reset signal representative of a timing of the first duration and the second duration, and a first data output to provide a first data signal, the flip-flop to;

responsive to the reset signal having a first reset state, configure the first data signal to a second data state that is the complement of the first data state;

responsive to the comparator signal having a first comparator state while the reset signal has a second reset state, configure the first data signal to the first data state and maintain the first data signal at the first data state until the reset signal is reconfigured to the first reset state; and

responsive to the comparator signal having a second comparator state while the reset signal has the second reset state, maintain a present data state of the first data signal until the reset signal is reconfigured to the first reset state; and

an enable circuit to configure the local enable signal to selectively disable the comparator based at least in part on the first data signal.

17. The LED driver of claim 16, wherein:

the comparator configures the comparator signal to the first comparator state responsive to the input signal having a voltage lower than the corresponding reference voltage and configures the comparator signal to the second comparator state responsive to the input signal having a voltage not lower than the corresponding reference voltage.

18. The LED driver of claim 16, wherein the enable circuit is to configure the local enable signal further based on a global enable signal.

19. The LED driver of claim 18, wherein the LED driver is to configure the global enable signal to a first enable state prior to configuring the reset signal to the first reset state and to configure the global enable signal to a second enable state concurrent with or after configuring the reset signal to the second reset state.

20. The LED driver of claim 16, further comprising:

a minimum select module configured to provide the minimum tail voltage of the tail voltages of the plurality of LED strings to the signal input over the first duration.