Soft Error Hard Electronic Circuit and Layout

• US 20100264953A1
• Filed: 04/19/2010
• Published: 10/21/2010
• Est. Priority Date: 01/15/2009
• Status: Active Grant

• Current Assignee: RCI Europe AB
• Original Assignee: Klas Olof Lilja
• Inventors: Lilja, Klas Olof
• Granted Patent: US 8,495,550 B2
• Time in Patent Office: Days
• US Class Current: 326/12
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H03K 19/00338 In field effect transistor circuits
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

This invention comprises a layout method to effectively protect electronic circuits against soft errors (non-destructive errors) and circuit cells, which are protected against soft errors. The invention applies a layout method to sequential and combinational logic to generate specific circuit cells with netlists and layouts which are hardened against single event generated soft-errors. It also devices methods of how two or more such cells should be laid out and placed relative to each other, in order to have the best global soft-error protection.

Claims

1. A sequential logic cell (also referred to as a latch), comprising four inverter circuits, each inverter comprising at least one p-type MOSFET and at least one n-type MOSFET, where the inverter have been connected as a Dual Interlocked Cell (DICE), the cell having four nets (numbered 1,2,3,4), each net connected to one inverter output and to two gates, such that the n'"'"'th net is connected to the output of the n'"'"'th inverter, to gate of the p-type MOSFET of the (n+1)'"'"'th inverter, and to the n-type MOSFET gate of the (n−

1)'"'"'th inverter, in a cyclic manner (such that when n=0, then n−

1 refers to the 4'"'"'th net, and when n=4 then n+1 refers to the first net), nets 1 and 3 carrying the same voltage state and net 2 and 4 carrying the inverse of the voltage state of net 1 and 3, each net having one p-type drain contact area (denoted p1, p2, p3, p4) and one n-type drain contact area (denoted n1, n2, n3, n4), these contact areas being the original drain contact areas, the MOSFETs of these contact areas being the original 8 MOSFETs, and the DICE circuit cell formed by these MOSFETs the original circuit cell, comprising;

a) an arrangement where the contact areas of each of the four nets, are placed along a line in the layout, and

b) the drain contact areas are placed along the line in the layout in any of the following orders;

n3, n4, p4, p1, n1, n2, p2, p3

n4, n3, p4, p3, n2, n1, p2, p1

n2, n3, p4, p3, n2, n1, p2, p1

n4, n1, n3, n2, p3, p2, p1, p4

n1, n4, n3, n2, p2, p3, p4, p1

n1, n4, n3, n2, p4, p3, p2, p1

n4, p4, n3, p3, n2, p2, n1, p1

and any order that can be derived naturally from these configuration, under consideration of the circuit symmetry, including cyclic permutations, or an interchange of the following drain contact area pairs [n1, n3], [n2, n4], [p1, p3], and [p2, p4].

2. The sequential logic cell according to claim 1, further comprising a first set of additional MOSFETs, said set of additional MOSFETs comprising one or more additional MOSFETs, that perform clocking in of a data into the sequential logic cell, comprising:

a) an arrangement where the drain contact areas of the first set of additional MOSFETs are placed along the same line as the drain contact areas of the original MOSFETs, and such that the drain contact areas of the first additional MOSFETs are either shared with, or placed adjacent to the original drain contact areas of the same type (n-type or p-type), to which they are connected.

3. The sequential logic cell according to claim 2 whereby the additional MOSFETs are added in such a way that they, to the extent permitted by the circuit netlist, keep the symmetry of the original sequential DICE circuit and layout from Claim 1, comprising:

a) an arrangement where the additional MOSFETs are added in such way that the same number and type of additional MOSFETs are connected in the same way to each of the original nets in the original circuit, or

b) an arrangement where the additional MOSFETs are added in such a way that the combined added MOSFETs to two first non-consecutive circuit nets in the original circuit (which carry the same signal), has the same number and type of additional MOSFETs, and the same connections, as the combined added MOSFETs to the two other non-consecutive circuit nets in the original circuit (which carry the opposite signal as the first two non-consecutive circuit nets).

4. A sequential logic cell according to claim 1, comprising:

a) an arrangement where a first additional n-type MOSFET is connected in series to each original n-type MOSFET in the DICE latch circuit; and

b) an arrangement where a second and a third n-type MOSFET is connected in series with each other, and in parallel to each of the original and first added n-type MOSFET, whereby the gate of the third added MOSFET of net 1 and 3 is connected to a data signal, the gate of the third added MOSFET of net 2 and 4 is connected to the inverse of said data signal, the gate of the second added MOSFET (for each net) is connected to a clocking signal, and the gate of the first added MOSFET to the inverse of said clocking signal; and

c) the drain contact areas of the added MOSFETs are either shared with, or placed adjacent to, the drain contact area, or the same type, of the original MOSFET to which they are connected.

5. A sequential logic cell according to claim 1, comprising:

a) an arrangement where a first additional p-type MOSFET is connected in series to each original p-type MOSFET in the DICE latch circuit; and

b) an arrangement where a second and a third p-type MOSFET is connected in series with each other, and in parallel to each of the original and first added p-type MOSFET, whereby the gate of the third added MOSFET of net 1 and 3 is connected to a data signal, the gate of the third added MOSFET of net 2 and 4 is connected to the inverse of said data signal, the gate of the first added MOSFET (for each net) is connected to a clocking signal, and the gate of the second added MOSFET to the inverse of said clocking signal; and

c) the drain contact areas of the added MOSFETs are either shared with, or placed adjacent to, the drain contact area, or the same type, of the original MOSFET to which they are connected.

6. A sequential logic cell according to claim 4 or claim 5, which contains further extra additional MOSFETs which are used to generate one or more nets carrying the inverse of the data signal and one or more nets carrying the inverse of the clocking signal, comprising:

a) An arrangement where the contact areas of the extra additional MOSFET are added to the layout in such a way that they minimize the disruption of the symmetry of the original layout; and

b) if of any of the extra additional MOSFETs is such, that a single event affecting a first contact area of one of these extra additional MOSFETs, and one other second contact area of the DICE element, can cause a change of the state of the whole element, then this first contact area is placed along the line in the layout at a position as far as possible from the second contact area.

7. A sequential logic cell according to claim 1, comprising:

a) an arrangement where two first additional n-type MOSFETs are connected in series to the original n-type MOSFET connected to node 1 and 2 in the DICE latch circuit, respectively, and two first p-type MOSFETs are connected in series to the original p-type MOSFET connected to node 1 and 4 in the DICE latch circuit, respectively, and for each of the two MOSFETs thus connected in series, a second and a third MOSFET, of the same type, is connected in series with each other, and in parallel to each the original and first additional MOSFET, at the positions in the circuit where the first additional MOSFET has been added, whereby the gates of the third added MOSFETs of net 1 are connected to a data signal, the gates of the third added MOSFETs of net 2 and 4 are connected to the inverse of said data signal, the gate of the second added n-type MOSFETs and first added p-type MOSFETs are connected to a clocking signal, and the gate of the first added n-type MOSFETS and second added p-type MOSFET to the inverse of said clocking signal, hence creating a filtering latch for the data and inverse data signal;

or

b) an arrangement the MOSFETs are added in an equivalent manner to 3 other nodes in the original DICE circuit, e.g., by cyclic permutation; and

c) the drain contact areas of the added MOSFETs are either shared with, or placed adjacent to, the drain contact area, or the same type, of the original MOSFET to which they are connected.

11. An electronic circuit comprising five circuit nodes forming two inter-coupled DICE latches of the type in claim 1), whereby these two DICE latches share 3 of the storage nodes and the individual devices connected to these 3 nodes, and whereby, when, in the inter-coupled DICE circuit, the signals from two different nodes, which are not shared, would be connected to the same gate of a MOSFET whose drain is connected to one of the shared nodes, then this MOSFET is replaced by two parallel MOSFETs of the same type, and one of the signals is connected to one of the two parallel MOSFETs and the other signal to the other parallel MOSFET, said electronic circuit with added means to clock in a data signal, said circuit containing an error correction method which corrects for single errors, comprising:

a) an arrangement where all drain contact areas in the circuit are arranged in a line in the layout; and

b) where, if px is the drain of the p-type MOSFET, and nx the drain of the n-type MOSFET drain, which is connected to node x, and the adjacent nodes in the DICE schematic are ordered 0, 1, 2, 3,4, the drain contact areas along the line are ordered are ordered according to the methodology in US patent application US2009/0184733, and claim 1) of this invention. This includes the following node orders;

[n0, p0, p1, n1, n2, p2, p3, n3, n4, p4], as well as any cyclic permutation of this order, and any order where the following nodes are interchanged;

odd n-type, even n-type, odd p-type, odd n-type pairs. It also includes the order [n4, p4, n3, p3, n2, p2, n1, p1, n0, p0]. Furthermore, when an n-type or p-type drain contact occurs twice in the layout, the two nodes of the same type can be inserted next to each other, or next to other nodes whereby the rule above in this claim (adjacent nodes having opposite effect) always is maintained. One such arrangement order is [n3, n0, p0, p1, n1, n2, p2, p3, n3, n4, p4, p1].

12. An electronic circuit comprising 6 storage nodes forming three inter-coupled DICE latches, whereby each of the 3 DICE latches are made up of (non-identical) sets of 4 of the 6 circuit nodes, and the first DICE latch share 3 circuit nodes with the second DICE latch, the second DICE latch share 3 circuit nodes with the third DICE latch, and where the devices connected only to shared nodes are also shared, and whereby, when, in the inter-coupled DICE circuit, the signals from two different nodes, would be connected to the same gate of a MOSFET, then this MOSFET is replaced by two parallel MOSFETs of the same type, and one of the signals is connected to one of the two parallel MOSFETs and the other signal to the other parallel MOSFET, said electronic circuit with added means to clock in a data signal, said electronic circuit containing an error correction method which corrects for single errors, comprising:

a) an arrangement where all drain contact areas in the circuit are arranged in a line in the layout; and

b) where, if px is the drain of the p-type MOSFET, and nx the drain of the n-type MOSFET drain, which is connected to node x, and the adjacent nodes in the schematic are ordered 0, 1, 2, 3,4,5 the drain contact areas along the line are ordered according to the methodology in US patent US2009/0184733, and claim 1) of this invention. This includes the following node orders;

[n0,p0,p1,n1,n2,p2,p3,n3,n4,p4,p5,n5], as well as any cyclic permutation of this order, and any order where the following nodes are interchanged;

odd n-type, even n-type, odd p-type, odd n-type pairs. It also includes the order [n5,p5,n4,p4,n3,p3,n2,p2,n1,p1,n0,p0]. Furthermore, when an n-type or p-type drain contact occurs twice in the layout, the two nodes of the same type can be inserted next to each other, or next to other nodes whereby the rule above in this claim (adjacent nodes having opposite effect) always is maintained. One such arrangement order is [n3,n0,p0,p1,n1,n2,p2,p3,n3,n4,p4,p5,n5,n4].

14. A method for laying out an electronic circuit wherein the electronic circuit comprises circuit cells, said method comprising:

a) a layout generation of each cell such that the error cross-section is reduced in certain directions using the method in claims 1 and 2 of U.S. patent application Ser. No. 12/354,655; and

b) an identification of one or more groups of cells, for which a simultaneous error in two or more cells in the group would cause an error, or reduced performance, in the overall circuit function, and placing all cells in such a group such that they are all positioned in a direction of reduced cross-section of the other cells in the group.

8. A duplicated combinational circuit wherein the circuit carries a primary and a redundant copy of the data signal, the redundant signal being the inverse of the primary signal, and where each logic gate consists of a regular logic gate, operating on the primary signal, and of an inverse logic gate, being the inverse of the regular logic gate, operating on the redundant (inverse) signal, said inverse logic gate, having the function provided by inverting every signal in the truth-table for the regular logic gate, comprising:

a) a layout arrangement wherein the combined regular and inverse logic gate is laid out such that there is no straight line between two contact areas in the layout, for which a single event have the same effect on the state of the circuit, unless there is another contact area in between the first two contact areas, for which a single event has the opposite effect on the state of the circuit, i.e., if a single event affecting a first contact area has the effect of creating an error on the primary signal, and a single event on a second node has the effect of creating an error on the redundant (inverse signal), then one, or more, third contact areas, for which a single event has the opposite effect of the that on the first or second contact areas, should be placed in between said first and second contact areas.

9. A duplicated combinational circuit, according to claim 8), wherein the primary logic gate is a NAND gate and the inverse redundant logic gate is a NOR gate.

10. A duplicated combinational circuit, compromising two inter-coupled c-elements, wherein one of the inputs of the first c-element is connected to a logic data input signal, and one of the inputs of the other c-element is connected to the inverse of said data signal, and the output of each c-element is connected to one of the inputs of the other c-element, comprising:

a) a layout arrangement where all the contact areas which are connected to nodes in the circuit element, are placed along a line in the layout; and

b) if px is the drain of the p-type MOSFET, and nx is the drain of the n-type MOSFET drain, which is connected to output node x, and the adjacent nodes in the schematic are ordered 0,1, the nodes along the line are ordered such that two nodes, for which a single event has the same effect on the circuit state, are always separated by another node that has the opposite effect on the circuit state. This includes the following node orders;

[p0, p1, n1, n0], as well as any cyclic permutation of this order, and any order where the following nodes are interchanged;

odd n-type, even n-type, odd p-type, odd n-type pairs.

13. An electronic circuit comprising duplicated combinational logic cells of claims 8 and 9, and sequential logic cells and filter cells of claims 7 and 10, as well as other cells, wherein:

a) a set of connected duplicated combinational cells are placed relative to each other such that a single event that affects two or more cells cannot create an error, which is such that it can create an error in the overall circuit function, on both of the signals carried by the duplicated logic; and

b) at the end of the set of cells is placed a filter, which is such that it would prevent an error on one of the two duplicated logic signals to propagate, hence decoupling the cells in the set from cells outside the set, with respect to the action on the overall circuit, of a single event that (simultaneously) affects the set and any other cell, not part of the set.

15. A method for laying out an electronic circuit, comprising:

a) an arrangement where for some, first, n-type contact areas, a second n-type MOSFET is added next to said contact area, whereby the first drain contact area forms the drain contact area of the second MOSFET, and the source contact area of the second MOSFET is connected to the high power (VDD), and the gate of the second MOSFET is always connected to the low power (VSS); and

b) an arrangement where for some, first, p-type contact areas, a second p-type MOSFET is added next to said contact area, whereby the first drain contact area forms the drain contact area of the second MOSFET, and the source contact area of the second MOSFET is connected to the low power (VSS), and the gate of the second MOSFET is always connected to the high power (VDD).