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Soft Error Hard Electronic Circuit and Layout

  • US 20100264953A1
  • Filed: 04/19/2010
  • Published: 10/21/2010
  • Est. Priority Date: 01/15/2009
  • Status: Active Grant
First Claim
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1. A sequential logic cell (also referred to as a latch), comprising four inverter circuits, each inverter comprising at least one p-type MOSFET and at least one n-type MOSFET, where the inverter have been connected as a Dual Interlocked Cell (DICE), the cell having four nets (numbered 1,2,3,4), each net connected to one inverter output and to two gates, such that the n'"'"'th net is connected to the output of the n'"'"'th inverter, to gate of the p-type MOSFET of the (n+1)'"'"'th inverter, and to the n-type MOSFET gate of the (n−

  • 1)'"'"'th inverter, in a cyclic manner (such that when n=0, then n−

    1 refers to the 4'"'"'th net, and when n=4 then n+1 refers to the first net), nets 1 and 3 carrying the same voltage state and net 2 and 4 carrying the inverse of the voltage state of net 1 and 3, each net having one p-type drain contact area (denoted p1, p2, p3, p4) and one n-type drain contact area (denoted n1, n2, n3, n4), these contact areas being the original drain contact areas, the MOSFETs of these contact areas being the original 8 MOSFETs, and the DICE circuit cell formed by these MOSFETs the original circuit cell, comprising;

    a) an arrangement where the contact areas of each of the four nets, are placed along a line in the layout, andb) the drain contact areas are placed along the line in the layout in any of the following orders;

    n3, n4, p4, p1, n1, n2, p2, p3n4, n3, p4, p3, n2, n1, p2, p1n2, n3, p4, p3, n2, n1, p2, p1n4, n1, n3, n2, p3, p2, p1, p4n1, n4, n3, n2, p2, p3, p4, p1n1, n4, n3, n2, p4, p3, p2, p1n4, p4, n3, p3, n2, p2, n1, p1and any order that can be derived naturally from these configuration, under consideration of the circuit symmetry, including cyclic permutations, or an interchange of the following drain contact area pairs [n1, n3], [n2, n4], [p1, p3], and [p2, p4].

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