LOW POWER ACTIVE MATRIX DISPLAY

• US 20100265168A1
• Filed: 04/15/2009
• Published: 10/21/2010
• Est. Priority Date: 04/15/2009
• Status: Active Grant

• Current Assignee: Vusiongroup
• Original Assignee: W5 Networks, Inc. (VusionGroup SA)
• Inventors: Neugebauer, Charles F.
• Granted Patent: US 8,248,341 B2
• Time in Patent Office: Days
• US Class Current: 345/87
• CPC Class Codes: G09G 2300/0417 Special arrangements specific to the use of low carrier mobility technology
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 2310/06 Details of flat display driving waveforms
• CPC Class Codes: G09G 2310/063 Waveforms for resetting the whole screen at once
• CPC Class Codes: G09G 2320/0214 with crosstalk due to leakage current of pixel switch in active matrix panels
• CPC Class Codes: G09G 2320/046 Dealing with screen burn-in prevention or compensation of the effects thereof
• CPC Class Codes: G09G 2330/023 using energy recovery or conservation
• CPC Class Codes: G09G 2330/04 Display protection
• CPC Class Codes: G09G 2380/04 Electronic labels
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3651 using multistable liquid crystals, e.g. ferroelectric liquid crystals
• CPC Class Codes: G09G 3/3659 the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

Described herein are systems and methods for the reduction of power consumption and mitigation of device stress accumulation in low frequency refreshed Liquid Crystal Displays (LCDs). In an exemplary embodiment, two or more transistors in series are used to hold charge on an LCD pixel. To prevent negative stress on the transistors, the transistors are alternately driven to an “on” state so that no one transistor sees a long “off” time. In another embodiment, circuits and signaling waveforms for performing frame writing and stress mitigation are provided that minimize dynamic power consumption and static power consumption in peripheral ESD circuits.

Claims

1. A method of operating a display circuit, the display circuit comprising a plurality of active matrix pixels connected to a common electrode and to a row driver circuit through a plurality of row signals, the method comprising:

modulating the common electrode;

writing a plurality of charges to the active matrix pixels; and

modulating substantially all of the row signals with substantially the same polarity and amplitude as one or more modulations of the common electrode to substantially preserve the active matrix pixel charges and reduce power loss in the row driver circuit.

2. The method of claim 1, further comprising modulating substantially all of the row signals with substantially the same polarity and amplitude as a negative modulation of the common electrode.

3. A display circuit for a pixel array, comprising:

a row and column driver; and

a plurality of pixel circuits coupled to the row and column driver, wherein each pixel circuit comprises at least two transistors in series connected to a pixel of a Liquid Crystal Display (LCD);

wherein the row and column driver is configured to write a new frame onto the LCD by applying first negative gate voltages and positive gate voltages to the transistors of the pixel circuits to form conduction paths to the pixels of the LCD and sending charges to the pixels through the conduction paths, and between frame write operations, for each pixel circuit, applying second negative gate voltages which are higher than said first negative gate voltages.

4. The display circuit of claim 3, wherein the row driver is configured to apply the positive gate voltage to fewer than all of the transistors of the pixel circuit at a rate greater than the frame write operation rate.

5. The display circuit of claim 3, wherein the row and column driver is configured to update the frame of the LCD at a rate of 10 Hz or slower.

6. The display circuit of claim 3, wherein the row and column driver is configured to update the frame of the LCD at a rate of 1 Hz or slower.

7. The display circuit of claim 3, wherein the transistors comprise amorphous silicon hydrogenated thin film transistors (a-Si:

H TFTs).

8. A method of operating a display circuit, the display circuit comprising a plurality of transistors connected to pixels of a Liquid Crystal Display (LCD), the method comprising:

performing frame write operations, wherein each frame write operation updates a display image of the LCD, and comprises applying gate voltages to the transistors to program the pixels of the LCD;

modulating said gate voltages during the frame write operations to substantially maintain charge on the pixels of the LCD; and

between frame write operations, applying gate voltage modulations to the transistors of the display circuit to keep the transistor channels substantially free of electronic charge.