MULTI-CHIP PACKAGES PROVIDING REDUCED SIGNAL SKEW AND RELATED METHODS OF OPERATION

• US 20100265751A1
• Filed: 02/23/2010
• Published: 10/21/2010
• Est. Priority Date: 04/15/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Hong, YoungSeok
• Granted Patent: US 8,331,121 B2
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48147 with an intermediate bond, e.g. continuous wire daisy chain
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/484 Connecting portions
• CPC Class Codes: H01L 2224/4911 the connectors being bonded to at least one common bonding area, e.g. daisy chain
• CPC Class Codes: H01L 2224/49112 the connectors connecting a common bonding area on the semiconductor or solid-state body to different bonding areas outside the body, e.g. diverging wires
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83191 wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/85181 connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
• CPC Class Codes: H01L 2224/85186 connecting first outside the semiconductor or solid-state body, i.e. off-chip, reverse stitch
• CPC Class Codes: H01L 2224/85191 : connecting first both on and outside the semiconductor or solid-state body, i.e. regular and reverse stitches
• CPC Class Codes: H01L 2225/06506 : Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01083 : Bismuth [Bi]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H05K 2201/10515 : Stacked components
• CPC Class Codes: H05K 2201/1053 : Mounted components directly electrically connected to each other, i.e. not via the PCB
• CPC Class Codes: H05K 2203/049 : Wire bonding
• CPC Class Codes: H05K 2203/1316 : Moulded encapsulation of mounted components
• CPC Class Codes: H05K 3/284 : for encapsulating mounted components H05K1/185 takes precedence

Abstract

A packaged integrated circuit device includes a substrate including a conductive pad thereon, and a chip stack including a plurality of chips on the substrate. A primary conductive line electrically connects the pad on the substrate to a conductive pad on one of the plurality of chips in the chip stack. Secondary conductive lines electrically connect the pad on the one of the plurality of chips to respective conductive pads on ones of the plurality of chips above and below the one of the plurality of chips in the chip stack. The primary conductive line may be configured to transmit a signal from the pad on the substrate to the pad on the one of the plurality of chips in the chip stack. After receiving the signal at the one of the plurality of chips, the secondary conductive lines may be configured to transmit the signal from the one of the plurality of chips to the ones of the plurality of chips above and below the one of the plurality of chips in the chip stack at a same time. Related methods of operation are also discussed.

Claims

1. A packaged integrated circuit device, comprising:

a substrate including a conductive pad thereon;

a chip stack including a plurality of chips on the substrate;

a primary conductive line electrically connecting the pad on the substrate to a conductive pad on one of the plurality of chips in the chip stack; and

secondary conductive lines electrically connecting the pad on the one of the plurality of chips to respective conductive pads on ones of the plurality of chips above and below the one of the plurality of chips in the chip stack.

2. The device of claim 1, wherein the primary conductive line is configured to transmit a signal from the pad on the substrate to the pad on the one of the plurality of chips in the chip stack, and wherein the secondary conductive lines are configured to transmit the signal from the one of the plurality of chips to the ones of the plurality of chips above and below the one of the plurality of chips in the chip stack at a same time responsive to receiving the signal at the one of the plurality of chips.

3. The device of claim 2, wherein a first one of the secondary conductive lines connects the one of the plurality of chips to the ones of the plurality of chips thereabove in series, and wherein a second one of the secondary conductive lines connects the one of the plurality of chips to the ones of the plurality of chips therebelow in series such that, after receiving the signal at the one of the plurality of chips, a time delay for receiving the signal at ones of the plurality of chips that are similarly positioned on opposite sides of the one of the plurality of chips is substantially similar.

4. The device of claim 2, further comprising:

a ternary conductive line connecting one of the respective pads on a last one of the plurality of chips that is connected to one of the secondary conductive lines to a conductive pad on another one of the plurality of chips that is not directly thereon and configured to transmit the signal thereto; and

quaternary conductive lines connecting the conductive pad on the another one of the plurality of chips to respective conductive pads on ones of the plurality of chips in the chip stack above and below the another one of the plurality of chips and configured to simultaneously transmit the signal thereto.

5. The device of claim 1, wherein the signal transmitted via the primary and secondary conductive lines comprises at least one of an address signal, a data signal, and a command signal.

6. The device of claim 1, wherein the one of the plurality of chips is positioned in the chip stack near a middle position thereof such that each of the secondary conductive lines comprises a similar electrical length.

7. The device of claim 1, wherein the one of the plurality of chips and the chips therebelow define a first chip stack of a first multi-chip package, wherein the ones of the plurality of chips above the one of the plurality of chips define a second chip stack of a second multi-chip package to provide a package-on-package (PoP) structure, the second multi-chip package comprising:

a second substrate having the second chip stack thereon, the second substrate including a conductive pad thereon and external terminals electrically connected to the pad on the one of the plurality of chips in the first chip stack,

wherein one of the secondary conductive lines connects the pad on the second substrate to the plurality of chips of the second chip stack.

8. The device of claim 1, wherein the primary conductive line comprises a first primary conductive line connecting the pad on the substrate to a controller chip that is configured to control operations of the plurality of chips in the chip stack, and a second primary conductive line connecting the controller chip to the one of the plurality of chips in the chip stack.

9. The device of claim 1, wherein the primary conductive line comprises at least one of a wirebond and a through molded via (TMV) directly connecting the pad on the substrate to the one of the plurality of chips, and wherein the secondary conductive lines respectively comprise conductive vias extending through the ones of the plurality of chips above and below the one of the plurality of chips.

10. The device of claim 1, wherein the plurality of chips in the chip stack comprise one of flash memory, dynamic random access memory (DRAM), static random access memory (SRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM) chips.

11. The device of claim 10, wherein the plurality of chips in the chip stack comprises eight memory chips or more.

12. A memory storage device, comprising:

a controller;

a memory unit; and

a printed circuit board including the controller and the memory unit thereon and configured to provide communication therebetween,

wherein the memory unit comprises at least one packaged integrated circuit device according to claim 1.

13. An electronic system, comprising:

a processor;

a memory unit;

an input/output unit; and

a bus that communicatively couples the processor, the memory, and the input/output unit,

wherein at least one of the processor and the memory unit comprise at least one packaged integrated circuit device according to claim 1.

14. A method of operating an integrated circuit device including a substrate and a chip stack including a plurality of chips thereon, the method comprising:

transmitting a signal from a conductive pad on the substrate to one of the plurality of chips in the chip stack via a primary conductive line that connects the pad on the substrate to a conductive pad on one of the plurality of chips, wherein the one of the plurality of chips is not directly on the substrate; and

then

simultaneously transmitting the signal from the one of the plurality of chips to to ones of the plurality of chips above and below the one of the plurality of chips in the chip stack via secondary conductive lines that connect the pad on the one of the plurality of chips to respective conductive pads on the ones of the plurality of chips above and below the one of the plurality of chips in the chip stack.

15. The method of claim 14, wherein, simultaneously transmitting the signal via the secondary conductive lines comprises:

serially transmitting the signal to the ones of the plurality of chips above the one of the plurality of chips via a first one of the secondary conductive lines that connects the one of the plurality of chips to the ones of the plurality of chips thereabove; and

serially transmitting the signal to the ones of the plurality of chips below the one of the plurality of chips via a second one of the secondary conductive lines that connects the one of the plurality of chips to the ones of the plurality of chips therebelow,

wherein, after receiving the signal at the one of the plurality of chips, a time delay for receiving the signal is substantially similar for ones of the plurality of chips that are similarly positioned on opposite sides of the one of the plurality of chips.

16. The method of claim 14, further comprising:

transmitting the signal from one of the respective pads on a last one of the plurality of chips connected to one of the secondary conductive lines to a conductive pad on another one of the plurality of chips that is not directly thereon via a ternary conductive line; and

simultaneously transmitting the signal from the pad on the another one of the plurality of chips to respective conductive pads on ones of the plurality of chips in the chip stack above and below the another one of the plurality of chips via quaternary conductive lines.

17. The method of claim 14, wherein the signal comprises at least one of an address signal, a data signal, and a command signal.

18. The method of claim 14, wherein the one of the plurality of chips is positioned in the chip stack near a middle position thereof such that each of the secondary conductive lines comprises a similar electrical length.

19. The method of claim 14, wherein the one of the plurality of chips and the chips therebelow define a first chip stack of a first multi-chip package, wherein the ones of the plurality of chips above the one of the plurality of chips define a second chip stack of a second multi-chip package to provide a package-on-package (PoP) structure, the second multi-chip package comprising a second substrate having the second chip stack thereon, the second substrate including a conductive pad thereon and external terminals electrically connected to the pad on the last one of the plurality of chips in the first chip stack, wherein one of the secondary conductive lines connects the pad on the second substrate to the plurality of chips of the second chip stack.

20. The method of claim 14, wherein the primary conductive line comprises a first primary conductive line connecting the pad on the substrate to a controller chip that is configured to control operations of the plurality of chips in the chip stack, and a second primary conductive line connecting the controller chip to the one of the plurality of chips in the chip stack, and wherein transmitting the signal from the pad on the substrate to the one of the plurality of chips in the chip stack comprises:

transmitting a control signal from the substrate to the controller chip via the first primary conductive line; and

then

transmitting the signal from the controller chip to the one of the plurality of chips in the chip stack via the secondary conductive line.

21. The method of claim 14, wherein the primary conductive line comprises at least one of a wirebond and a through molded via (TMV) directly connecting the pad on the substrate to the one of the plurality of chips, and wherein the secondary conductive lines comprise respective conductive vias extending through the ones of the plurality of chips above and below the one of the plurality of chips.